Patrick D Weber

US Patent:

20130058148, Mar 7, 2013

Filed:

Feb 24, 2012

Appl. No.:

13/404995

Inventors:

Allan CANTLE - Westlake Village CA, US
Patrick WEBER - Oxnard CA, US
Mark GILLIAM - Thousand Oaks CA, US
Prashant JOSHI - Thousand Oaks CA, US

International Classification:

G11C 5/06

US Classification:

365 63

Abstract:

Solid state memory modules are disclosed having increased density for module size/footprint. Different embodiments also provide for improved interconnect arrangements between the memory modules and the corresponding field programmable gate array (FPGA), micro-processor (μP), or application-specific integrated circuit (ASIC). These interconnects can provide for greater module interconnect flexibility, operating speed and operating efficiency. Some memory module embodiments according to the present invention comprises a plurality of solid state memory devices arranged on a first printed circuit board. A second printed circuit board is on and electrically connected to the first printed circuit board, with the second printed circuit board having a pin-out for direct coupling to a host device.