Paul E Gray

US Patent:

7673213, Mar 2, 2010

Filed:

Aug 12, 2005

Appl. No.:

11/203683

Inventors:

Keith Michael Chugg - La Canada CA, US
Paul Kingsley Gray - San Diego CA, US

Assignee:

Trellisware Technologies, Inc. - San Diego CA

International Classification:

H03M 13/00
H03M 13/03

US Classification:

714755, 714790

Abstract:

Methods, apparatuses, and systems are presented for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits, processing the outer encoded bits using an interleaver and a single parity check (SPC) module to produce intermediate bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, processing the inner encoded bits using a puncture module to produce punctured bits, and combining the data bits and the punctured bits to produce encoded outputs. Methods, apparatuses, and systems are also presented for performing data decoding based on soft channel metrics derived from a channel using various iterative techniques.

US Patent:

7958425, Jun 7, 2011

Filed:

Feb 16, 2005

Appl. No.:

11/060081

Inventors:

Keith Michael Chugg - La Canada CA, US
Paul Kingsley Gray - San Diego CA, US
Georgios Dimitrios Dimou - San Diego CA, US
Phunsak Thiennviboon - San Diego CA, US

Assignee:

Trelliware Technologies, Inc. - San Diego CA

International Classification:

H03M 13/00

US Classification:

714755

Abstract:

The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.

US Patent:

20070259075, Nov 8, 2007

Filed:

May 4, 2006

Appl. No.:

11/418012

Inventors:

Paul Gray - Venice CA, US

International Classification:

B65D 85/00

US Classification:

426091000

Abstract:

A confection support holder is disclosed. The confection support holder includes, a support chamber, a resilient insulation cover, an outer support cover, a plurality of protrusions and a reservoir. The resilient insulation cover includes a second resilient insulation side contacting said support chamber and a first resilient insulation side. The outer support cover includes a first cover side contacting a confection and a second cover side contacting said first resilient insulation side, a bottom cover portion, a top cover portion and a body cover portion. The plurality of protrusions contact said first cover side of said outer support cover and contact said confection, providing support. The reservoir, including a plurality of ridge members, is sealed to said bottom cover portion, providing protection from said confection dripping.