Paul C Pierce

US Patent:

D479217, Sep 2, 2003

Filed:

Jul 30, 2002

Appl. No.:

29/164739

Inventors:

Michelle Lew Ho-Cheun - Trevose Park, SG
Bee Lay Khoo - Johor Bahru, MY
Ee Fong Lee - Singapore, SG
Joshua Maruska - Bellevue WA
Paul Pierce - Grayslake IL
Timothy Sutherland - Gurnee IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

1403

US Classification:

D14138

US Patent:

D485833, Jan 27, 2004

Filed:

Jan 31, 2003

Appl. No.:

29/175205

Inventors:

Joshua Maruska - Bellevue WA
Paul M. Pierce - Grayslake IL
Joseph Graceffa - Boulder CO

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

1403

US Classification:

D14248

US Patent:

D487886, Mar 30, 2004

Filed:

Jun 24, 2003

Appl. No.:

29/185208

Inventors:

Michelle Lew Ho-Cheun - Trevose Park, SG
Bee Lay Khoo - Johor Bahru, MY
Ee Fong Lee - Singapore, SG
Joshua Maruska - Bellevue WA
Paul Pierce - Grayslake IL
Timothy Sutherland - Gurnee IL

Assignee:

Motoraola, Inc. - Schaumburg IL

International Classification:

1403

US Classification:

D14138

US Patent:

7058750, Jun 6, 2006

Filed:

May 10, 2000

Appl. No.:

09/569100

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7343442, Mar 11, 2008

Filed:

Jun 6, 2006

Appl. No.:

11/422542

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7603508, Oct 13, 2009

Filed:

Jan 14, 2008

Appl. No.:

12/013595

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7930464, Apr 19, 2011

Filed:

Aug 28, 2009

Appl. No.:

12/549491

Inventors:

Linda J. Rankin - Portland OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710306

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

8255605, Aug 28, 2012

Filed:

Mar 30, 2011

Appl. No.:

13/076041

Inventors:

Linda J. Rankin - Portland OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Shanghai, CN
Kai Cheng - Portland OR, US
Richard H Hofsheier - Banks OR, US
Nitin Y. Borkar - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710306

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.