Peter Y Chang

Address:

6402 Dry Clf Cv, Austin, TX 78731

VIN:

5TDYK3EH5CS050035

Make:

TOYOTA

Model:

HIGHLANDER

Year:

2012

US Patent:

7649569, Jan 19, 2010

Filed:

May 24, 2005

Appl. No.:

11/135724

Inventors:

Peter Chang - Hurst TX, US
Rajitha Padakanti - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 9/475

US Classification:

348512, 348516, 348521, 348497

Abstract:

System and method for digitally correcting time base errors in video display systems. A preferred embodiment comprises 1) correcting time base errors in a first portion of a horizontal line of video information, wherein the first correcting makes use of an error estimate for the horizontal line of video information and a preceding horizontal line of video information, 2) correcting time base errors in a second portion of a horizontal line of video information, wherein the second correcting makes use of an error estimate for the horizontal line of video information, and 3) repeating the first correcting and the second correcting for remaining horizontal lines of video information in the digitized video signal.

US Patent:

63300346, Dec 11, 2001

Filed:

Oct 30, 1998

Appl. No.:

9/183243

Inventors:

Karl Renner - Dallas TX
Peter Chang - Hurst TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 945
H04N 324
H03L 700

US Classification:

348536

Abstract:

A microprocessor controlled color phase locked loop is provided which provides flexibility and adaptability for different television standards and sampling rates. Color burst phase error and color burst amplitude information are stored in data registers located at the output of the phase locked loop's low pass filter rather than at the output of the color demodulator.

US Patent:

20230049454, Feb 16, 2023

Filed:

Oct 10, 2022

Appl. No.:

17/962585

Inventors:

- Dallas TX, US
Shinri Inamori - Kawasaki-shi, JP
Jagadeesh Sankaran - Allen TX, US
Peter Chang - Colleyville TX, US

International Classification:

G06F 15/80
G06F 9/30
G06F 9/38
G06F 9/345
G06F 15/76

Abstract:

A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

US Patent:

20210004349, Jan 7, 2021

Filed:

Sep 21, 2020

Appl. No.:

17/026412

Inventors:

- Dallas TX, US
Shinri Inamori - Kawasaki-shi, JP
Jagadeesh Sankaran - Allen TX, US
Peter Chang - Colleyville TX, US

International Classification:

G06F 15/80
G06F 9/30
G06F 9/38
G06F 9/345
G06F 15/76

Abstract:

A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.