Peter Joseph Michels

US Patent:

6487623, Nov 26, 2002

Filed:

Apr 30, 1999

Appl. No.:

09/303369

Inventors:

Theodore F. Emerson - Houston TX
Vincent Nguyen - Sugarland TX
Peter Michels - Cypress TX
Steve Clohset - Fair Oaks CA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

710302, 714 7, 714 42

Abstract:

A computer system adapted for hot-pluggable components such as memory modules that may be replaced, upgraded and/or added without disturbing normal operation of the computer system. A failing memory module may be replaced by copying its contents to a new memory module in a background operation while the computer system runs its operating system and applications programs. When all contents are copied to the new memory module, the failing memory module may be removed without having to shut down the computer system. Computer system memory may be upgraded or added to by inserting the new memory module(s) into vacant disconnected memory connectors, whereupon the computer system automatically recognizes the new memory module(s), synchronously connects the new memory module(s) to the computer system memory bus, initializes the new memory module(s), and then notifies the operating system that the new memory module(s) is available, all without disturbing normal operation of the computer system.

US Patent:

6581162, Jun 17, 2003

Filed:

Dec 31, 1996

Appl. No.:

08/777615

Inventors:

Michael F. Angelo - Houston TX
Peter J. Michels - Plano TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

H04K 900

US Classification:

713193, 380277

Abstract:

A secure environment for entering and storing information necessary to conduct encryption processes. In a computer system according to the invention, session keys, passwords, and encryption algorithms are maintained in a secure memory space such as System Management Mode (SMM) memory. In one disclosed embodiment of the invention, a user password is entered via a secure keyboard channel. The password is maintained in a secure memory space that is not accessible during normal computer operation. In addition to the user password, optional node identification information is stored in secure memory. The node identification information is appended to the user password, and both are subsequently encrypted by an encryption algorithm and encryption keys that are also stored in secure memory. Following the encryption process, the encrypted password and node identification information are communicated directly from secure memory to network interface circuitry for communication over a network. In another disclosed embodiment of the invention, data entered in a secure manner is utilized as an encryption key (or to generate an encryption key) for securely encrypting packets of data prior to communicating the data over a computer network.

US Patent:

7746785, Jun 29, 2010

Filed:

Aug 22, 2006

Appl. No.:

11/507670

Inventors:

Peter Michels - Cupertino CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 12/56
H04J 3/02
H03K 19/173

US Classification:

370235, 370391, 370532, 370538, 326 38

Abstract:

An apparatus and method are provided to perform a time multiplexing logic in a module, are provided including identifying a driving flop and a receiving flop in the module, receiving a modified input signal, and identifying a worst case timing path for the modified input signal to transmit from the driving flop to the receiving flop. The time multiplexing logic of the apparatus and method further identifies a predetermined point of the worst case timing path, and inserts a logic unit at the predetermined point allowing the time multiplexing logic circuit to process and output the modified input signal at a maximum frequency.

US Patent:

7770095, Aug 3, 2010

Filed:

Aug 2, 2006

Appl. No.:

11/497293

Inventors:

Peter Michels - Cupertino CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 13/00
H04L 1/00

US Classification:

714799, 714781

Abstract:

An apparatus and method are provided including a point-to-point cluster link configured to receive a data packet and determines a cyclic redundancy code check for the data packet. The point-to-point cluster link is configured to add a cyclic redundancy code check bit to the data packet transmitted to the point-to-point inter-cluster link, to clear the cyclic redundancy code check bit when the data packet is received, and to sample a cyclic redundancy code window to identify a corrupted data packet.

US Patent:

20020129186, Sep 12, 2002

Filed:

May 14, 2002

Appl. No.:

10/145553

Inventors:

Theodore Emerson - Houston TX, US
Vincent Nguyen - Sugarland TX, US
Steve Clohset - Sacramento CA, US
Peter Michels - Cypress TX, US

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F013/00

US Classification:

710/302000

Abstract:

A computer system adapted for hot-pluggable components such as memory modules that may be replaced, upgraded and/or added without disturbing normal operation of the computer system. A failing memory module may be replaced by copying its contents to a new memory module in a background operation while the computer system runs its operating system and applications programs. When all contents are copied to the new memory module, the failing memory module may be removed without having to shut down the computer system. Computer system memory may be upgraded or added to by inserting the new memory module(s) into vacant disconnected memory connectors, whereupon the computer system automatically recognizes the new memory module(s), synchronously connects the new memory module(s) to the computer system memory bus, initializes the new memory module(s), and then notifies the operating system that the new memory module(s) is available, all without disturbing normal operation of the computer system.

US Patent:

20070053290, Mar 8, 2007

Filed:

Aug 16, 2006

Appl. No.:

11/504634

Inventors:

Peter Michels - Cupertino CA, US

International Classification:

H04L 12/26

US Classification:

370230000

Abstract:

An apparatus and method to optimize latency and bandwidth in a system include a queue configured to receive control data packets of a control stream, and an arbiter. The arbiter is operatively connected to the queue and configured to set a threshold level defining a priority to transmit and process each control data packet, to read header attribute information associated with the control data packet, and to determine, based on the header attribute information included in the control data packet, a length of each control data packet. The arbiter is configured to compare the length of each control data packet with the threshold level to prioritize transmission of the control data packets.

US Patent:

6182187, Jan 30, 2001

Filed:

Apr 7, 1993

Appl. No.:

8/044241

Inventors:

B. Tod Cox - Houston TX
Peter J. Michels - Cypress TX
Michael R. Kluth - Tomball TX
Jeffrey S. Watters - Beaverton OR

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1200

US Classification:

711 5

Abstract:

A computer system having a system ROM comprising a flash or bulk EPROM replacing a block flash or boot block EPROM, and a second ROM to store the primary boot code. In a first embodiment, a single block EPROM is replaced with a bulk EPROM and a ROM, where the ROM is preferably a one-time programmable ROM. The primary boot code is copied into the ROM thereby preventing its erasure. The bulk EPROM is reprogrammed if desired. Separate decode logic detects an address to the primary boot code and enables the ROM. In a second system using a block EPROM and a bulk EPROM as the system ROM, the block EPROM is replaced with a bulk EPROM, and the primary boot code is copied into both bulk EPROMs, preferably at mirrored locations. An external switch is provided with appropriate logic, so that the user may select between either of the bulk EPROMs to boot the system. Thus, if the system is unable to boot from one of the bulk EPROMs, the user may flip the switch to access the primary boot code from the other bulk EPROM.

US Patent:

60981342, Aug 1, 2000

Filed:

Dec 31, 1996

Appl. No.:

8/775130

Inventors:

Peter Michels - Plano TX
Christopher J. Pettey - Houston TX
Thomas R. Seeman - Tomball TX
Brian S. Hausauer - Spring TX

Assignee:

Compaq Computer Corp. - Houston TX

International Classification:

G06F 1338
G06F 1517

US Classification:

710108

Abstract:

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i. e. , a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus.