Peter Hong Xiao

US Patent:

6344877, Feb 5, 2002

Filed:

Jun 12, 1997

Appl. No.:

08/873539

Inventors:

Sudhir Muniswamy Gowda - Ossining NY
Hyun Jong Shin - Ridgefield CT
Peter Hong Xiao - San Jose CA
Jungwook Yang - West Nyack NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04N 964

US Classification:

348245, 348308, 2502081

Abstract:

Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.

US Patent:

6538695, Mar 25, 2003

Filed:

Nov 4, 1998

Appl. No.:

09/185796

Inventors:

Peter Hong Xiao - San Jose CA
Evan Y. Wang - Fremont CA

Assignee:

IC Media Corporation - San Jose CA

International Classification:

H04N 964

US Classification:

348245, 348308, 2502081

Abstract:

An on-chip FPN calibration method and circuits scheme applying a reference voltage signal to an array of calibration pixels coupled to a sensor matrix. Two data values are read from each bit line and used to calculate an offset and a gain error for a pixel column. A reference offset and a reference gain error value are then generated by computing the average offset and the average gain error from the collected offset and gain error values of each bit line. Calibration data for each bit line then comprises an offset difference and a gain error difference, the offset difference comprising the difference between the offset value for that bit line and the reference offset, and the gain error difference comprising the gain error difference between the gain error for that bit line and the reference gain error. The calibration data for each bit line is then stored in on-chip volatile memory and is used later under normal operation to compensate for the FPN effect.

US Patent:

7050029, May 23, 2006

Filed:

Apr 26, 2001

Appl. No.:

09/842988

Inventors:

Jemm Y. Liang - San Jose CA, US
Peter Xiao - San Jose CA, US

Assignee:

JPS Group Holdings, Ltd. - Tortola

International Classification:

G09G 3/36

US Classification:

345 96, 345 99, 345209

Abstract:

Two separate power supplies are employed to generate electrical potentials for driving row and column electrodes of LCDs. One or more energy storage devices are preferably used together with the two power supplies for generating such potentials. In the first phase, the energy storage devices are charged and in the second phase, such devices and the power supplies are employed to generate the appropriate potentials for driving the row and column electrodes. Such schemes permit the column electrodes to be driven through a voltage range much smaller than the convention IAPT driving schemes and vastly reduces the power consumption by the driver. The total voltage dynamic range experienced by the driver circuit is comparable to the IAPT driving scheme.

US Patent:

7106318, Sep 12, 2006

Filed:

Apr 28, 2000

Appl. No.:

09/561737

Inventors:

Jemm Y. Liang - San Jose CA, US
Peter Xiao - San Jose CA, US

Assignee:

JPS Group Holdings, Ltd. - Tortola

International Classification:

G09G 5/00

US Classification:

345211, 345 95

Abstract:

Two separate power supplies are employed to generate electrical potentials for driving row and column electrodes of LCDs. One or more energy storage devices are preferably used together with the two power supplies for generating such potentials. In the first phase, the energy storage devices are charged and in the second phase, such devices and the power supplies are employed to generate the appropriate potentials for driving the row and column electrodes. Such schemes permit the column electrodes to be driven through a voltage range much smaller than the convention IAPT driving schemes and vastly reduces the power consumption by the driver. The total voltage dynamic range experienced by the driver circuit is comparable to the IAPT driving scheme.

US Patent:

7411452, Aug 12, 2008

Filed:

Nov 13, 2006

Appl. No.:

11/559395

Inventors:

Chih-Wen Lu - Jhumen Village, TW
Peter H. Xiao - Belmont CA, US

Assignee:

New Vision Micro Inc. - Tortola

International Classification:

H03F 3/45

US Classification:

330253, 330261

Abstract:

A low DC power rail-to-rail buffer amplifier is suitable for liquid crystal display application. The buffer amplifier comprises: a dc bias stage, a pair of complementary differential amplifiers, a second stage amplifier, and output stage. The dc bias stage is used for the dc bias of the differential amplifiers and the second stage to obtain a rail-to-rail operation. This buffer amplifier can be operated in the power supply ranges of 5. 5 V to the breakdown voltage. Simulated results show that the circuit draws only 5. 3 μA static current.

US Patent:

8094721, Jan 10, 2012

Filed:

Dec 29, 2005

Appl. No.:

11/323602

Inventors:

Xudong Song - Fremont CA, US
Peter Xiao - Fremont CA, US
Lei Zhu - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04N 7/12

US Classification:

37524013, 37524012

Abstract:

In one embodiment, the methods and apparatuses detect a current macroblock and an adjacent macroblock within the scene; detect a mode of the adjacent macroblock; and select a skip mode as a mode for the current macroblock based on the mode of the adjacent macroblock.

US Patent:

8249070, Aug 21, 2012

Filed:

Dec 29, 2005

Appl. No.:

11/323285

Inventors:

Xudong Song - Fremont CA, US
Peter Xiao - Fremont CA, US
Lei Zhu - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

370391, 37039564

Abstract:

In one embodiment, the methods and apparatuses detect a network bandwidth; detect a sequence of frames; determine a motion based on the sequence of frames; set a target bit rate for the sequence of frames based on the network bandwidth; and set a frame rate for the sequence of frames based on the motion of the sequence of frames, wherein the target bit rate and the frame rate are utilized to process the sequence of frames.

US Patent:

7362294, Apr 22, 2008

Filed:

Sep 27, 2002

Appl. No.:

10/256687

Inventors:

Jemm Y. Liang - San Jose CA, US
Peter Xiao - San Jose CA, US
Juan Shih-Hsin - Junghe, TW

Assignee:

JPS Group Holdings, Ltd - Tortola

International Classification:

G09G 3/36

US Classification:

345 89, 345 94, 345 95

Abstract:

In a passive liquid crystal display, frames or fields are displayed for different time periods to achieve gray scale. The voltage pulses applied to the column electrodes have substantially constant values during row scanning periods or field scanning periods to reduce power consumption. The lines of the display may be divided into odd and even fields in an interlaced configuration to suppress flicker and to further reduce power consumption by reducing frame rate.