Phillip A Stout

US Patent:

20070196988, Aug 23, 2007

Filed:

Feb 23, 2006

Appl. No.:

11/360796

Inventors:

Mehul Shroff - Austin TX, US
Mark Hall - Austin TX, US
Paul Grudowski - Austin TX, US
Tab Stephens - Buda TX, US
Phillip Stout - Austin TX, US
Olubunmi Adetutu - Austin TX, US

International Classification:

H01L 21/336

US Classification:

438299000, 438197000, 438303000

Abstract:

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack () formed over a substrate (), thereby forming an etched gate () having a vertical sidewall profile by implanting the gate stack () with a nitrogen () and a dopant () and then heating the polysilicon gate stack () at a selected temperature using rapid thermal annealing () to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack () creates an etched gate () having more idealized vertical gate sidewall profiles.

US Patent:

7811891, Oct 12, 2010

Filed:

Jan 13, 2006

Appl. No.:

11/331958

Inventors:

Marius K. Orlowski - Austin TX, US
Olubunmi O. Adetutu - Austin TX, US
Phillip J. Stout - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438285, 438590, 438718, 257E21198, 257E21201

Abstract:

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack () formed over a substrate (), thereby forming an etched gate () having a vertical sidewall profile (). By constructing the gate stack () with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile () may be obtained.