Rakesh Kirit Patel

US Patent:

6335635, Jan 1, 2002

Filed:

May 24, 2000

Appl. No.:

09/578252

Inventors:

Rakesh Patel - Cupertino CA
John Turner - Santa Cruz CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326101, 326 39

Abstract:

Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended device is readily scalable to allow quick transitions to next generation technologies.

US Patent:

6342794, Jan 29, 2002

Filed:

Jul 24, 2000

Appl. No.:

09/621939

Inventors:

John E. Turner - Santa Cruz CA
Rakesh H. Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190185

US Classification:

326 68, 326 81, 326 86

Abstract:

A technique and circuitry to interface an integrated circuit to other integrated circuits in a mixed-voltage mode environment. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage level. The input and output signals to and from the integrated circuit will be compatible with the external supply level. Specifically, a level shifter ( ) or similar conversion circuit is used to convert voltages compatible with the internal supply level to be compatible with the external supply level.

US Patent:

6344758, Feb 5, 2002

Filed:

Jul 22, 1999

Appl. No.:

09/359196

Inventors:

John E. Turner - Santa Cruz CA
Rakesh H. Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190175

US Classification:

326 86, 326 81, 326 68, 326 38

Abstract:

A technique and circuitry to interface an integrated circuit to other integrated circuits in a mixed-voltage mode environment. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage level. The input and output signals to and from the integrated circuit will be compatible with the external supply level. Specifically, a level shifter ( ) or similar conversion circuit is used to convert voltages compatible with the internal supply level to be compatible with the external supply level.

US Patent:

6351144, Feb 26, 2002

Filed:

Jul 13, 2000

Appl. No.:

09/615926

Inventors:

Wei-Jen Huang - Burlingame CA
Rakesh Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 738

US Classification:

326 41, 326 47, 257723, 257724, 361783

Abstract:

A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps.

US Patent:

6353552, Mar 5, 2002

Filed:

Mar 26, 2001

Appl. No.:

09/817951

Inventors:

Stephen P. Sample - Saratoga CA
Michael R. Butts - Portland OR
Kevin A. Norman - Belmont CA
Rakesh H. Patel - Cupertino CA
Chao Chiang Chen - Cupertino CA

Assignee:

Altera Corporation - San Jose CA
Quickturn Design Systems, Inc. - Mountain View CA

International Classification:

G11C 700

US Classification:

365154, 36518908

Abstract:

Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.

US Patent:

6366120, Apr 2, 2002

Filed:

Mar 2, 2000

Appl. No.:

09/517146

Inventors:

James Schleicher - Santa Clara CA
James Park - San Jose CA
Bruce Pedersen - San Jose CA
Tony Ngai - Campbell CA
Wei-Jen Huang - Burlingame CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190177

US Classification:

326 41, 326 40, 326 39

Abstract:

A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

US Patent:

6407576, Jun 18, 2002

Filed:

Mar 2, 2000

Appl. No.:

09/516921

Inventors:

Tony Ngai - Campbell CA
Bruce Pedersen - San Jose CA
James Schleicher - Santa Clara CA
Wei-Jen Huang - Burlingame CA
Michael Hutton - Palo Alto CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA
Peter J. Kazarian - Cupertino CA
Andrew Leaver - Palo Alto CA
David W. Mendel - Sunnyvale CA
Jim Park - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 39, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

US Patent:

6414518, Jul 2, 2002

Filed:

Nov 24, 1999

Appl. No.:

09/449166

Inventors:

Rakesh H. Patel - Cupertino CA
John E. Turner - Santa Cruz CA
John D. Lam - Fremont CA
Wilson Wong - San Francisco CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 1900

US Classification:

326101, 326 41, 257207

Abstract:

A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.