Rakesh Patel

US Patent:

6335635, Jan 1, 2002

Filed:

May 24, 2000

Appl. No.:

09/578252

Inventors:

Rakesh Patel - Cupertino CA
John Turner - Santa Cruz CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326101, 326 39

Abstract:

Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended device is readily scalable to allow quick transitions to next generation technologies.

US Patent:

6351144, Feb 26, 2002

Filed:

Jul 13, 2000

Appl. No.:

09/615926

Inventors:

Wei-Jen Huang - Burlingame CA
Rakesh Patel - Cupertino CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 738

US Classification:

326 41, 326 47, 257723, 257724, 361783

Abstract:

A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps.

US Patent:

6414518, Jul 2, 2002

Filed:

Nov 24, 1999

Appl. No.:

09/449166

Inventors:

Rakesh H. Patel - Cupertino CA
John E. Turner - Santa Cruz CA
John D. Lam - Fremont CA
Wilson Wong - San Francisco CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 1900

US Classification:

326101, 326 41, 257207

Abstract:

A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.

US Patent:

6433585, Aug 13, 2002

Filed:

Sep 22, 1999

Appl. No.:

09/401145

Inventors:

Rakesh H. Patel - Cupertino CA
John E. Turner - Santa Cruz CA
Wilson Wong - San Francisco CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19094

US Classification:

326 83, 326 86, 326 87, 326121

Abstract:

An input/output driver for interfacing directly with a voltage at a pad ( ) which is above a supply voltage ( ) for the input/output driver. This may be referred to as an âovervoltage condition. â For example, if the supply voltage is 3. 3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator ( ) for preventing leakage current paths.

US Patent:

6515507, Feb 4, 2003

Filed:

Jun 29, 2000

Appl. No.:

09/607569

Inventors:

Rakesh H. Patel - Cupertino CA
Thomas H. White - Santa Clara CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 738

US Classification:

326 38, 326 80, 36518521

Abstract:

An integrated circuit has one or more external control pins to control and indicate which of two or more different VCC or other voltage levels will be used. The control pin receives a logic signal, high or low, and draws zero static power. A user can use the integrated circuit with two or more VCC voltage levels by indicating which voltage level at the control pins. In a specific embodiment, the integrated circuit has nonvolatile memory cells such as EEPROM or Flash cells that a configurable and reconfigurable using on-chip programming circuitry. The programming circuitry may generate and use superhigh or high voltages, higher than the VCC voltage.

US Patent:

6563343, May 13, 2003

Filed:

Apr 30, 2002

Appl. No.:

10/136944

Inventors:

Rakesh H. Patel - Cupertino CA
John E. Turner - Santa Cruz CA
John D. Lam - Fremont CA
Wilson Wong - San Francisco CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190175

US Classification:

326 87, 326112

Abstract:

A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.

US Patent:

6570404, May 27, 2003

Filed:

Mar 26, 1997

Appl. No.:

08/824535

Inventors:

Kevin A. Norman - Belmont CA
Rakesh H. Patel - Cupertino CA
Stephen P. Sample - Saratoga CA
Michael R. Butts - Portland OR

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 39, 326 40, 326 41, 326 38

Abstract:

A programmable logic device architecture. This programmable logic architecture includes a first logic block ( ) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface ( ), which interfaces with the first logic block ( ), for performing JTAG functions, configuring the first logic block ( ), initializing the first logic block ( ), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block ( ) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network ( ). The first logic block ( ) includes a plurality of second logic blocks ( ) which may be programmably coupled using a second programmable interconnect network ( ). The second programmable interconnect network ( ) may be programmably coupled to the first programmable interconnect network ( ). Furthermore, the plurality of second logic blocks ( ) include a plurality of third logic blocks ( ) which may be programmably coupled using a third programmable interconnect network ( ).

US Patent:

6583646, Jun 24, 2003

Filed:

May 16, 2001

Appl. No.:

09/860028

Inventors:

Rakesh H. Patel - Cupertino CA
John E. Turner - Santa Cruz CA
Wilson Wong - San Francisco CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 190175

US Classification:

326 80, 326 68, 326 81, 326 86

Abstract:

An input/output driver for interfacing directly with a voltage at a pad which is above a supply voltage for the input/output driver. This may be referred to as an âovervoltage condition. â For example, if the supply voltage is 3. 3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator for preventing leakage current paths.