Raymond K Leung

US Patent:

58674233, Feb 2, 1999

Filed:

Apr 10, 1997

Appl. No.:

8/838799

Inventors:

Ashok Kapoor - Palo Alto CA
Alex Owens - Los Gatos CA
Thomas R. Wik - Livermore CA
Raymond T. Leung - Palo Alto CA
V. Swamy Irrinki - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1156

US Classification:

365168

Abstract:

A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.

US Patent:

57843287, Jul 21, 1998

Filed:

Dec 23, 1996

Appl. No.:

8/779999

Inventors:

V. Swamy Irrinki - Milpitas CA
Ashok Kapoor - Palo Alto CA
Raymond Leung - Palo Alto CA
Alex Owens - Los Gatos CA
Thomas R. Wik - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

365222

Abstract:

A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized.

US Patent:

58089322, Sep 15, 1998

Filed:

Dec 23, 1996

Appl. No.:

8/779991

Inventors:

V. Swamy Irrinki - Milpitas CA
Ashok Kapoor - Palo Alto CA
Raymond T. Leung - Palo Alto CA
Alex Owens - Los Gatos CA
Thomas R. Wik - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1124
G11C 1156

US Classification:

365150

Abstract:

A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

US Patent:

50457268, Sep 3, 1991

Filed:

May 16, 1990

Appl. No.:

7/524329

Inventors:

Raymond T. Leung - Palo Alto CA

Assignee:

North American Philips Corporation - Tarrytown NY

International Classification:

H03K 1712

US Classification:

307466

Abstract:

A programming circuit for an array of bipolar transistors which is selectable by row and column decoders to form a selected logic circuit, programming being effected by thermal links respectively connected to the respective transistors and which undergo a change in conductive state when subjected to a programming current of sufficient magnitude. The programming circuit includes a row driver having an FET gate which in response to a row address selection pulse turns on a bipolar transistor (Q1), the FET gate otherwise maintaining Q1 off. Transistor Q1 forms a Darlington pair with any of the transistors in the corresponding row of the array which are turned on. The transistors in respective columns of the array are connected in common by respective column conductors to respective transmission gates, each transmission gate including another Darlington bipolar pair driven by a CMOS inverter. The inverter opens the transmission gate in response to a strobe pulse which is concurrent with a column selection pulse from the column decoder, but otherwise maintains the transmission gate closed. A significant reduction in power consumption, and consequent heat dissipation, is achieved because the row drivers and transmission gates for non-selected rows and columns do not require quiescent operating current, and programming current for a selected transistor is supplied in a path comprising only bipolar Darlington pairs.

US Patent:

59826592, Nov 9, 1999

Filed:

Dec 23, 1996

Appl. No.:

8/779998

Inventors:

V. Swamy Irrinki - Milpitas CA
Thomas R. Wik - Livermore CA
Raymond T. Leung - Palo Alto CA
Ashok Kapoor - Palo Alto CA
Alex Owens - Los Gatos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1156

US Classification:

365168

Abstract:

A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

US Patent:

57611106, Jun 2, 1998

Filed:

Dec 23, 1996

Appl. No.:

8/779992

Inventors:

V. Swamy Irrinki - Milpitas CA
Ashok Kapoor - Palo Alto CA
Raymond T. Leung - Palo Alto CA
Alex Owens - Los Gatos CA
Thomas R. Wik - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1714

US Classification:

365100

Abstract:

A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

US Patent:

58479902, Dec 8, 1998

Filed:

Dec 23, 1996

Appl. No.:

8/779993

Inventors:

V. Swamy Irrinki - Milpitas CA
Ashok Kapoor - Palo Alto CA
Raymond T. Leung - Palo Alto CA
Alex Owens - Los Gatos CA
Thomas R. Wik - Livermore CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1100

US Classification:

365154

Abstract:

A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

US Patent:

20150369855, Dec 24, 2015

Filed:

Jun 23, 2015

Appl. No.:

14/748228

Inventors:

- Mountain View CA, US
Thu Nguyen - Palo Alto CA, US
Shih-Yao Christine Sun - San Jose CA, US
Raymond Tak-Hoi Leung - Palo Alto CA, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G01R 31/26
G06F 17/50

Abstract:

A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.