Raymond Kao Fai Leung

US Patent:

58674233, Feb 2, 1999

Filed:

Apr 10, 1997

Appl. No.:

8/838799

Inventors:

Ashok Kapoor - Palo Alto CA
Alex Owens - Los Gatos CA
Thomas R. Wik - Livermore CA
Raymond T. Leung - Palo Alto CA
V. Swamy Irrinki - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1156

US Classification:

365168

Abstract:

A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.

US Patent:

50457268, Sep 3, 1991

Filed:

May 16, 1990

Appl. No.:

7/524329

Inventors:

Raymond T. Leung - Palo Alto CA

Assignee:

North American Philips Corporation - Tarrytown NY

International Classification:

H03K 1712

US Classification:

307466

Abstract:

A programming circuit for an array of bipolar transistors which is selectable by row and column decoders to form a selected logic circuit, programming being effected by thermal links respectively connected to the respective transistors and which undergo a change in conductive state when subjected to a programming current of sufficient magnitude. The programming circuit includes a row driver having an FET gate which in response to a row address selection pulse turns on a bipolar transistor (Q1), the FET gate otherwise maintaining Q1 off. Transistor Q1 forms a Darlington pair with any of the transistors in the corresponding row of the array which are turned on. The transistors in respective columns of the array are connected in common by respective column conductors to respective transmission gates, each transmission gate including another Darlington bipolar pair driven by a CMOS inverter. The inverter opens the transmission gate in response to a strobe pulse which is concurrent with a column selection pulse from the column decoder, but otherwise maintains the transmission gate closed. A significant reduction in power consumption, and consequent heat dissipation, is achieved because the row drivers and transmission gates for non-selected rows and columns do not require quiescent operating current, and programming current for a selected transistor is supplied in a path comprising only bipolar Darlington pairs.

US Patent:

20150369855, Dec 24, 2015

Filed:

Jun 23, 2015

Appl. No.:

14/748228

Inventors:

- Mountain View CA, US
Thu Nguyen - Palo Alto CA, US
Shih-Yao Christine Sun - San Jose CA, US
Raymond Tak-Hoi Leung - Palo Alto CA, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G01R 31/26
G06F 17/50

Abstract:

A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

US Patent:

20150365075, Dec 17, 2015

Filed:

Jun 11, 2015

Appl. No.:

14/737288

Inventors:

- Mountain View CA, US
Thu Nguyen - Palo Alto CA, US
Raymond Tak-Hoi Leung - Palo Alto CA, US

International Classification:

H03K 3/011
H03K 3/356

Abstract:

A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.