Richard P Hess

US Patent:

6813527, Nov 2, 2004

Filed:

Nov 20, 2002

Appl. No.:

10/300185

Inventors:

Richard Hess - Glendale AZ

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G05B 902

US Classification:

700 82, 700 3, 700 21, 700 79, 700 81, 709208, 709209, 709210, 709211, 710110

Abstract:

A control system architecture suitably includes sufficient computation redundancy and control command management to isolate and recover a faulted processor and/or to recover all processing units in the redundant system without adverse effects. Computational redundancy may be provided with multiple processors and/or processing units within computers or computing platforms. In addition to isolating and recovering from internal faults, various embodiments allow computing units to detect faults in other system elements such as sensors, adaptors, actuators and/or effectors. Further embodiments may also include one or more actuator adaptor units that detect faults in other system components and issue discrete instructions to trigger a recovery. In some embodiments, the recovery is performed within one or two computing frames, or otherwise in a short enough time period so as to have only minimal affects, if any, on system performance or redundancy.

US Patent:

7698511, Apr 13, 2010

Filed:

May 19, 2005

Appl. No.:

11/132860

Inventors:

Richard F. Hess - Glendale AZ, US
Kent A. Stange - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 11/00
G11C 7/10

US Classification:

711154, 711162, 711100, 711101, 711161, 711167, 714 2, 714 5, 714 6, 36518905, 36518908

Abstract:

An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.

US Patent:

7725215, May 25, 2010

Filed:

May 4, 2006

Appl. No.:

11/381608

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00
G06F 7/00
B64C 19/00

US Classification:

701 1, 701 3, 701 29, 701 31, 701 36, 244 751, 244194, 714 2, 714 11

Abstract:

A real-time multi-tasking digital control system with rapid recovery capability is disclosed. The control system includes a plurality of computing units comprising a plurality of redundant processing units, with each of the processing units configured to generate one or more redundant control commands. One or more internal monitors are employed for detecting data errors in the control commands. One or more recovery triggers are provided for initiating rapid recovery of a processing unit if data errors are detected. The control system also includes a plurality of actuator control units each in operative communication with the computing units. The actuator control units are configured to initiate a rapid recovery if data errors are detected in one or more of the processing units. A plurality of smart actuators communicates with the actuator control units, and a plurality of redundant sensors communicates with the computing units.

US Patent:

7765427, Jul 27, 2010

Filed:

May 4, 2006

Appl. No.:

11/381637

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00

US Classification:

714 10

Abstract:

A monitoring system and methods are provided for a distributed and recoverable digital control system. The monitoring system generally comprises two independent monitoring planes within the control system. The first monitoring plane is internal to the computing units in the control system, and the second monitoring plane is external to the computing units. The internal first monitoring plane includes two in-line monitors. The first internal monitor is a self-checking, lock-step-processing monitor with integrated rapid recovery capability. The second internal monitor includes one or more reasonableness monitors, which compare actual effector position with commanded effector position. The external second monitor plane includes two monitors. The first external monitor includes a pre-recovery computing monitor, and the second external monitor includes a post recovery computing monitor. Various methods for implementing the monitoring functions are also disclosed.

US Patent:

7793147, Sep 7, 2010

Filed:

Jul 18, 2006

Appl. No.:

11/458301

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00

US Classification:

714 13, 714 12, 714 16

Abstract:

A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

US Patent:

7971095, Jun 28, 2011

Filed:

Feb 16, 2005

Appl. No.:

11/058764

Inventors:

Richard Hess - Glendale AZ, US
Gerald B. Kelly - Glendale AZ, US
Randy Rogers - Phoenix AZ, US
Kent A. Stange - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00

US Classification:

714 15

Abstract:

System and methods for providing a recoverable real time multi-tasking computer system are disclosed. In one embodiment, a system comprises a real time computing environment, wherein the real time computing environment is adapted to execute one or more applications and wherein each application is time and space partitioned. The system further comprises a fault detection system adapted to detect one or more faults affecting the real time computing environment and a fault recovery system, wherein upon the detection of a fault the fault recovery system is adapted to restore a backup set of state variables.

US Patent:

8036805, Oct 11, 2011

Filed:

Nov 26, 2007

Appl. No.:

11/945037

Inventors:

Timothy D. Mahoney - Chandler AZ, US
Scot E. Griffiths - Glendale AZ, US
Larry J. Yount - Scottsdale AZ, US
Richard F. Hess - Glendale AZ, US
Brendan Hall - Eden Prairie MN, US
Devesh Bhatt - Maple Grove MN, US
William M. McMahon - Tucson AZ, US
John Teager - Tucson AZ, US
Philip E. Rose - Tucson AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 7/00

US Classification:

701100, 701 99, 701 3

Abstract:

A distributed engine control system is provided. The engine control system includes first and second engine data concentrators. Each of the first and second engine data concentrators include a processor module, a signal conditioning module coupled to the processor module, a data transfer module coupled to the processor module, and a data bus coupled between the first and second engine data concentrators and a hydro-mechanical unit (HMU).

US Patent:

8260492, Sep 4, 2012

Filed:

May 4, 2006

Appl. No.:

11/381652

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/08
G06F 11/20

US Classification:

701 343, 701 337, 714 15, 714 20, 714E11007, 714E1103, 714E11055

Abstract:

A method and system for redundancy management is provided for a distributed and recoverable digital control system. The method uses unique redundancy management techniques to achieve recovery and restoration of redundant elements to full operation in an asynchronous environment. The system includes a first computing unit comprising a pair of redundant computational lanes for generating redundant control commands. One or more internal monitors detect data errors in the control commands, and provide a recovery trigger to the first computing unit. A second redundant computing unit provides the same features as the first computing unit. A first actuator control unit is configured to provide blending and monitoring of the control commands from the first and second computing units, and to provide a recovery trigger to each of the first and second computing units. A second actuator control unit provides the same features as the first actuator control unit.