Robert Lee Gilmore

US Patent:

20200105652, Apr 2, 2020

Filed:

Nov 19, 2019

Appl. No.:

16/688057

Inventors:

- San Diego CA, US
Shreepad Amar Panth - Atlanta GA, US
Yang Du - Carlsbad CA, US
Robert Philip Gilmore - Poway CA, US

International Classification:

H01L 23/498
H01L 21/768

Abstract:

A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

US Patent:

20140131885, May 15, 2014

Filed:

Jan 29, 2013

Appl. No.:

13/753193

Inventors:

- San Diego CA, US
Shreepad A. Panth - Atlanta GA, US
Yang Du - Carlsbad CA, US
Robert P. Gilmore - Poway CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 23/498
H01L 21/768

US Classification:

257774, 438667

Abstract:

A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.