Robert Alan Hopkins

US Patent:

7636361, Dec 22, 2009

Filed:

Sep 27, 2005

Appl. No.:

11/242113

Inventors:

Jo C. Ebergen - San Francisco CA, US
Justin M. Schauer - Palo Alto CA, US
Robert D. Hopkins - Hayward CA, US
Ivan E. Sutherland - Santa Monica CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 12/28

US Classification:

3703954, 370236

Abstract:

One embodiment of the present invention provides a system that asynchronously controls sending data items from a sender to a receiver. This system includes a set of sending FIFOs, a set of receiving FIFOs, as well as a shared data path between the sender and the receiver. The system also includes a set of control paths that operate in parallel between the sender and the receiver, wherein a given control path controls the transmission of data items between a corresponding sending FIFO and a corresponding receiving FIFO through the shared data path. The system further includes a round-robin scheduling mechanism which activates one control path at a time in a predetermined sequence. An activated control path asynchronously controls the sending of a data item from a corresponding sending FIFO to a corresponding receiving FIFO. By operating the control paths in parallel in the predetermined sequence, the system does not have to wait a request-acknowledge cycle time between the sender and the receiver before sending consecutive data items through the shared data path, but can instead send multiple data items through the shared data path within a single request-acknowledge cycle time.

US Patent:

7750709, Jul 6, 2010

Filed:

Jan 5, 2007

Appl. No.:

11/651221

Inventors:

Justin M. Schauer - San Francisco CA, US
Robert D. Hopkins - Hayward CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H03H 11/26

US Classification:

327264, 327261, 327268, 327276, 327277, 327278, 438141, 438142

Abstract:

One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.

US Patent:

8130821, Mar 6, 2012

Filed:

May 18, 2006

Appl. No.:

11/437287

Inventors:

Robert D. Hopkins - Hayward CA, US
Ronald Ho - Mountain View CA, US
William S. Coates - Los Gatos CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H04B 3/46

US Classification:

375233, 375232, 375291, 375288

Abstract:

An integrated circuit containing a communication channel is described. This communication channel includes a transmit circuit configured to transmit signals using a voltage-mode driver, a receive circuit, and a capacitive link that couples the transmit circuit to the receive circuit. The communication channel includes a filter with a capacitive-summing junction to equalize signals communicated between the transmit circuit and the receive circuit.

US Patent:

8644759, Feb 4, 2014

Filed:

Jan 6, 2009

Appl. No.:

12/349011

Inventors:

Justin M. Schauer - San Francisco CA, US
Robert David Hopkins - Hayward CA, US
Robert J. Drost - Los Altos CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H04B 5/00

US Classification:

455 411, 36518532, 36518521, 330253, 330288, 330261, 330277, 257369, 257290, 257314, 257323, 257319

Abstract:

Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.