Robert K Moss

Address:

20218 N 273 Ave, Buckeye, AZ 85396

VIN:

5FNRL387X7B085684

Make:

HONDA

Model:

ODYSSEY

Year:

2007

US Patent:

6366530, Apr 2, 2002

Filed:

Sep 28, 2001

Appl. No.:

09/965947

Inventors:

David O. Sluiter - Boulder CO
Robert W. Moss - Longmont CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 804

US Classification:

365240, 365233, 365239, 365221, 36518905, 36523006, 36518902

Abstract:

A digital logic circuit, such as a FIFO memory, includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a â2-hotâ encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

US Patent:

6496043, Dec 17, 2002

Filed:

Dec 13, 2001

Appl. No.:

10/020327

Inventors:

Robert W. Moss - Longmont CO
Peter Korger - Frederick CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 2500

US Classification:

327 12, 327163

Abstract:

A phase measurement circuit includes first and second complementary clock strobe inputs, a local clock input and a sample clock output. A programmable delay line is coupled between the local clock input and the sample clock output and has a plurality of propagation delay settings. First and second toggle circuits are clocked by the first and second clock strobe inputs, respectively, and each has a toggle output that changes state when clocked by the respective first or second clock strobe input. A capture latch circuit has first and second data inputs coupled to the toggle outputs of the first and second toggle circuits, respectively, has first and second capture outputs, and is clocked by the sample clock output. A synchronizer circuit has first and second data inputs coupled to the first and second capture outputs, respectively, has first and second synchronized capture outputs, and is clocked by the local clock input.

US Patent:

6509762, Jan 21, 2003

Filed:

Aug 8, 2002

Appl. No.:

10/215397

Inventors:

Robert W. Moss - Longmont CO
Peter Korger - Frederick CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 2500

US Classification:

327 12, 327199

Abstract:

A method and apparatus are provided for capturing data read from a memory device that is aligned with respect to a clock strobe signal originating from the memory device, which has constraints with respect to a local clock signal supplied to the memory device. The apparatus includes a circuit for capturing the data read from the memory device relative to the clock strobe signal to produce captured read data, a circuit for latching the captured read data relative to a sample clock signal, and a circuit for measuring a phase difference between the sample clock signal and the clock strobe signal and adjusting a phase of the sample clock signal as a function of the phase difference.

US Patent:

6600681, Jul 29, 2003

Filed:

Jun 10, 2002

Appl. No.:

10/165920

Inventors:

Peter Korger - Frederick CO
Robert W. Moss - Longmont CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

365193, 365194, 365233

Abstract:

A method an apparatus are provided for calibrating a mask signal which is used for masking a data strobe signal that is received from a memory device with read data. According to the method, one or more read operations are performed with the memory device, and the data strobe signal is sampled at a plurality of different time delays relative to a local clock signal to produce a plurality of data strobe sample values. The plurality of data strobe sample values are searched to identify a temporal location within a preamble phase of the data strobe sample values and one of the time delays that corresponds to the temporal location. A delay at which the mask signal is disabled in response to a read operation is then set relative to the local clock signal based on the time delay corresponding to the temporal location.

US Patent:

6646929, Nov 11, 2003

Filed:

Dec 5, 2001

Appl. No.:

10/012986

Inventors:

Robert W. Moss - Longmont CO
Peter Korger - Frederick CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

365194, 365193

Abstract:

Methods and associated structure for realignment of returned read data from the memory component to the memory controller to adjust for phase shift in the memory devices supplied strobe signals due to propagation delays and other layout, fabrication and environmental factors. The realignment features of the present invention impose a calibrated delay on the memory controllers clock signal used to sample registered read data from the memory components. By so adjusting the alignment of returned read data with respect to the memory controllers clock, the present invention obviates the need for an asynchronous FIFO as is presently commonly practiced in the art to avoid such phase shifts between memory components and associated memory controllers.

US Patent:

6725306, Apr 20, 2004

Filed:

Feb 27, 2002

Appl. No.:

10/083833

Inventors:

Russell B. Stuber - Boulder CO
Robert W. Moss - Longmont CO
David O. Sluiter - Superior CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1338

US Classification:

710107, 710108, 710110, 710112, 710 57

Abstract:

A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

US Patent:

6741096, May 25, 2004

Filed:

Jul 2, 2002

Appl. No.:

10/188880

Inventors:

Robert W. Moss - Longmont CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 19173

US Classification:

326 37, 326 94, 710124, 710120, 710123, 710117, 713502, 713400, 711158, 711154

Abstract:

Circuits and associated methods for operation thereof for gathering real-time statistical information regarding operation of the arbiter circuit in a particular system application. The real-time statistical information so gathered is useful for off-line analysis by a system designer for determining optimal configuration and parameter values associated with operation of a particular arbiter in a specific system application. In a first exemplary preferred embodiment, a timer circuit associated with the arbiter measures a predetermined period of time during which statistical data is to be gathered. Counter circuits associated with the arbiter count the number of occurrences of events of interest to the designer during the time period measured by the timer circuit. Each counter circuit preferably senses and counts a particular event of interest to the designer.

US Patent:

6798186, Sep 28, 2004

Filed:

May 8, 2002

Appl. No.:

10/141998

Inventors:

Peter Korger - Frederick CO
Robert W. Moss - Longmont CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 23175

US Classification:

324 7654, 324 731

Abstract:

A method and apparatus are provided for testing linearity of two or more programmable delay chains in an integrated circuit. A first delay chain is successively programmed to a first sequence of delay settings and, for each delay setting in the first sequence, a second delay chain is successively programmed to a second sequence of delay settings. The second sequence sweeps a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. For each delay setting of the second delay chain, a logic transition is applied to inputs of the first and second delay chains and the output of one of the first and second delay chains is latched as a function of the output of the other of the first and second delay chains to produce a sample value. The sample values produced for each delay setting in the first sequence are monitored to determining whether the logic transition occurs in the sample values within an expected time window.