Samuel S Choi

US Patent:

20070159465, Jul 12, 2007

Filed:

Jan 10, 2006

Appl. No.:

11/328214

Inventors:

Samuel Choi - La Palma CA, US

International Classification:

G06F 3/02

US Classification:

345168000

Abstract:

A keyboard for an information processing machine, such as personal computer, is designed so that each alphanumeric key has a rectangular upper surface of 17 mm to 20 mm in width and 20 mm to 25 mm in length. The distance between the upper surfaces of each key is set as 6 to 10 mm. These sizes are bigger than an average key board to allow an easy operation by a user with bigger body. The keyboard has actuators thereon arranged in a conventional keyboard distribution. But, the whole keyboard set is separated into two pieces of equal size and has apparently different configuration. One upper corner of each piece of the keyboard is pivotally connected to one end of a metal arm with a pivot joint. The other ends of two metal arms are connected each other via another pivot joint. This configuration enables a user adjusting the angle and span between the two pieces of a keyboard to maintain a more comfortable position than using conventional keyboard. A document to be typed can be placed between the two pieces of the keyboard of the current application.

US Patent:

20140070363, Mar 13, 2014

Filed:

Sep 10, 2012

Appl. No.:

13/608183

Inventors:

Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Naftali Eliahu Lustig - Croton on Hudson NY, US
Andrew H. Simon - Fishkill NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L 23/525
H01L 21/768

US Classification:

257530, 438381, 257E23147, 257E21592

Abstract:

An electronic anti-fuse structure, the structure including an Mlevel comprising a first Mmetal and a second Mmetal, a dielectric layer located above the Mlevel, an Mlevel located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mmetal and the second Mmetal, wherein the metallic element is insulated from both the first Mmetal and the second Mmetal.

US Patent:

20150255342, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721323

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 21/768

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20150255343, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721361

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 21/768

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20150255398, Sep 10, 2015

Filed:

May 26, 2015

Appl. No.:

14/721410

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton On Hudson NY, US
Andrew H. Simon - Fishkill NY, US

International Classification:

H01L 23/532

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

US Patent:

20140203435, Jul 24, 2014

Filed:

Jan 18, 2013

Appl. No.:

13/744705

Inventors:

- Armonk NY, US
Junjing Bao - Cedar Grove NJ, US
Griselda Bonilla - Fishkill NY, US
Samuel S. Choi - Beacon NY, US
James A. Culp - Newburgh NY, US
Thomas W. Dyer - Pleasant Valley NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Stephen E. Greco - Lagrangeville NY, US
Naftali E. Lustig - Croton on Hudson NY, US
Andrew H. Simon - Fishkill NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/768
H01L 23/532

US Classification:

257751, 438643

Abstract:

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.