Samuel T Ray

US Patent:

7081842, Jul 25, 2006

Filed:

Oct 18, 2004

Appl. No.:

10/967756

Inventors:

Louis Lu-Chen Hsu - Fishkill NY, US
James Stephen Mason - Eastleigh, GB
Gareth John Nicholls - Brockenhurst, GB
Philip Murfet - Stockbridge, GB
Samuel Ray - Morgan Hill CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 1/10

US Classification:

341121, 326 30, 326 82, 326 86, 326 90

Abstract:

Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

US Patent:

7279950, Oct 9, 2007

Filed:

Sep 27, 2005

Appl. No.:

11/235758

Inventors:

Stacy J. Garvin - Durham NC, US
Vernon R. Norman - Cary NC, US
Samuel T. Ray - Morgan Hill CA, US
Wayne A. Utter - Fuquay-Varina NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/00

US Classification:

327291, 327299

Abstract:

A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

US Patent:

7812643, Oct 12, 2010

Filed:

Feb 5, 2009

Appl. No.:

12/366005

Inventors:

Shashikala Govindu - Union City CA, US
Samuel Taylor Ray - Morgan Hill CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/20
H03K 19/094

US Classification:

326115, 327108

Abstract:

A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair.

US Patent:

20020175717, Nov 28, 2002

Filed:

May 25, 2001

Appl. No.:

09/865830

Inventors:

Samuel Ray - Morgan Hill CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K017/56

US Classification:

327/108000

Abstract:

An SCSI circuit which allows for the independent control of driver slew rate and amplitude with a linear shaped driver output voltage. The circuit comprises 1) a symmetrical H-Driver having at least four predrive controls; and 2) a predrive control circuit coupled to one of the predrive controls for independently varying the amplitude and rise time. The SCSI circuit is designed to utilize minimal space on the IO circuit pad, thereby conserving the amount of A space allotted by the silicon area on the integrated circuit chip.

US Patent:

20070279117, Dec 6, 2007

Filed:

Jun 27, 2007

Appl. No.:

11/769408

Inventors:

Hayden Cranford - Cary NC, US
Stacy Garvin - Durham NC, US
Vernon Norman - Cary NC, US
Samuel Ray - Morgan Hill CA, US
Wayne Utter - Fuquay-Varina NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/00

US Classification:

327291000

Abstract:

A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.

US Patent:

20230004181, Jan 5, 2023

Filed:

Sep 8, 2022

Appl. No.:

17/940865

Inventors:

- Yongin-City, KR
Samuel T. Ray - Morgan Hill CA, US

International Classification:

G05F 1/575
G05F 1/565
G05F 1/46

Abstract:

A voltage regulator that includes a first amplifier, a second amplifier, a summer, and a transistor is presented. The first amplifier has a first gain and a first frequency bandwidth, and is configured to generate a first voltage output. The second amplifier has a second gain that is lower than the first gain and a second frequency bandwidth that is higher than the first frequency bandwidth, and is configured to generate a second voltage output. The summer is configured to generate a summed voltage output. The transistor is connected to the summer and configured to generate a regulated voltage based on the summed voltage output of the summer.