Stephen A Clark

US Patent:

48070807, Feb 21, 1989

Filed:

Jun 15, 1987

Appl. No.:

7/062211

Inventors:

Stephen E. Clark - San Jose CA

Assignee:

Zilog, Inc. - Campbell CA

International Classification:

H02H 904

US Classification:

361 56

Abstract:

Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents generated by electrostatic discharge through handling or otherwise, is provided by a circuit structure at each input pad of an integrated circuit chip. One such feature includes the use of a barrier layer of polysilicon material to make an electrical contact between source and drain diffusions of a protective transistor and their respective aluminum conductors, in order to increase the amount of current that can be handled at such contacts without the aluminum conductor fusing though a diffusion into the substrate. Another such feature is to provide an initial, and perhaps only, protective transistor that has a very narrow channel between source and drain diffusions to allow a reversible breakdown to reduce the voltage across it to within, or nearly within, the maximum voltage that the protected thin gate oxide transistor can handle without being damaged. Further, current concentrations in the protective transistor are minimized by the use of elongated diffusions and associated solid elongated conductors having rounded corners.

US Patent:

50288199, Jul 2, 1991

Filed:

Jun 8, 1990

Appl. No.:

7/535403

Inventors:

Tom S. Wei - Campbell CA
Elisabeth Ekman - Campbell CA
Andre Walker - Campbell CA
Stephen Clark - Campbell CA

Assignee:

Zilog, Inc. - Campbell CA

International Classification:

H01L 2978
H03K 19094

US Classification:

307451

Abstract:

A CMOS N-channel, open-drain, pull-down buffer circuit is capable of pulling down voltages on an external pad in excess of the breakdown voltage of the individual N-channel field effect transistors in the buffer circuit. The circuit may be fabricated as part of a CMOS interated circuit in an industrial standard 1. 5 microns CMOS process. The higher voltage acceptance is effected by using two open-drain N-transistors in series such that the external voltage is divided among the two transistors. A parallel high voltage circuit to the external pad can be independently optimized to provide a lower impedance path and a higher endurance for electrostatic discharge. While the two-transistor voltage divider exposes one of the transistor' gate to ESD via another external terminal, enhanced ESD protection is effected by having a resistor in series between the gate and the external terminal.