Stephen R Olson

US Patent:

7422167, Sep 9, 2008

Filed:

Nov 26, 2003

Appl. No.:

10/721241

Inventors:

Stephen C. Olson - Norfolk MA, US

Assignee:

Sturtevant, Inc. - Hanover MA

International Classification:

B02B 1/00
B02B 5/02
B02C 11/08
B02C 21/00

US Classification:

241 39, 241 5, 241 38, 2412853

Abstract:

A fluid-energy mill for size reduction of a material includes a manifold defining a grinding chamber having a first radius extending from a center of the grinding chamber, a gas inlet, a feed inlet, and an outlet. The feed inlet is positioned such that the material enters the grinding chamber tangent to a second radius extending from the center and larger than the first radius. The fluid-energy mill includes a cover for enclosing the grinding chamber. The manifold defines a non-circular groove around the grinding chamber, and a seal is positioned within the groove. The grinding chamber is cycloid-shaped. The manifold defines a protective pocket and a barrier at a region where the material enters the grinding chamber. The feed inlet includes a feed gas inlet, a material funnel, and a venturi. An intersection of the feed gas inlet and the material funnel form an elliptical hole.

US Patent:

20030192972, Oct 16, 2003

Filed:

Apr 11, 2002

Appl. No.:

10/120929

Inventors:

Stephen Olson - Norfolk MA, US

International Classification:

B02C019/06

US Classification:

241/039000

Abstract:

A fluid-energy mill includes a one-piece manifold defining a grinding chamber, a gas inlet, a feed inlet, and a feed outlet. The fluid-energy mill includes a cover for enclosing the grinding chamber. The manifold defines a non-circular groove around the grinding chamber, and a seal is positioned within the groove. The grinding chamber is cycloid-shaped, and the feed inlet is positioned such that feed enters the grinding chamber tangent to a circle larger than a diameter of the grinding chamber. The manifold defines a protective pocket and a barrier at a region where feed enters the grinding chamber. The feed inlet includes a feed gas inlet, a feed particle funnel, and a venturi. An intersection of the feed gas inlet and the feed particle funnel form an elliptical hole.

US Patent:

D4304837, Sep 5, 2000

Filed:

Jul 20, 1999

Appl. No.:

D/108097

Inventors:

Cheung Kit Wah - Tai Po, HK
Pilar Tadrous - Jersey City NJ
Stephen T. Olson - Troy MI

Assignee:

Mitzi International - New York NY

International Classification:

0808

US Classification:

D 8382

US Patent:

56689675, Sep 16, 1997

Filed:

Sep 9, 1994

Appl. No.:

8/303853

Inventors:

Stephen W. Olson - Wilmington MA
James B. MacDonald - Dracut MA
Edward D. Mann - Methuen MA
James W. Petersen - Hudson NH

Assignee:

Wang Laboratories, Inc. - Billerica MA

International Classification:

G06F 1200

US Classification:

395842

Abstract:

Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register.

US Patent:

51231085, Jun 16, 1992

Filed:

Sep 11, 1989

Appl. No.:

7/405794

Inventors:

Stephen W. Olson - Wilmington MA
James B. MacDonald - Dracut MA

Assignee:

Wang Laboratories, Inc. - Lowell MA

International Classification:

G06F 938
G06F 9302
G06F 13396
G06F 1342

US Classification:

395800

Abstract:

An A output and a B output of a register file 16 are each provided to an associated multiplexer (18,20). Each multiplexer has as a further input a bus (CB00:31) that conveys a result from an ALU 22 via an ALU shifter 28. Outputs of the multiplexers are provided to corresponding A or B inputs of the ALU. Each multiplexer is controlled by an associated register file address comparator (24,26). The address comparators each have as an input corresponding register file A and B update and access addresses. The address comparators compare their associated register file update and access addresses to determine if the register file register selected for access is equal to the register file register selected for update. If these two addresses are found to be equal it is indicated that the result of an ALU operation during an instruction cycle N is to be used as an operand for an ALU operation during a cycle N+1. When this condition is detected the output of the associated address comparator enables the corresponding multiplexer select input to gate the ALU result directly to the corresponding input of the ALU, thereby effectively bypassing the register file.

US Patent:

54796288, Dec 26, 1995

Filed:

Oct 12, 1993

Appl. No.:

8/135037

Inventors:

Stephen W. Olson - Wilmington MA
James B. MacDonald - Dracut MA
Richard W. Lones - Amherst NH

Assignee:

Wang Laboratories, Inc. - Lowell MA

International Classification:

G06F 1210
G06F 1214

US Classification:

395416

Abstract:

A method, and circuitry that operates in accordance with the method, for generating an entry for a translation buffer in a data processor that employs virtual memory addressing. The method includes the first steps of storing a Faulted Virtual Address in a first register (96) and a Zone Table Address (ZTA) in a second register (94). In response to the execution of a micro-instruction, a next step forms an address in memory of a Zone Table Entry (ZTE) by selectively combining a first portion of the content of the first register with the content of the second register, while simultaneously testing the ZTA for physical address mapping. In response to an execution of a next micro-instruction, a next step accesses the ZTE with the formed address, and forms an address in memory of a Segment Table Entry (STE) by selectively combining a second portion the content of the first register with a content of the ZTE, while simultaneously testing the ZTE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the STE with the formed address, and forms an address in memory of a Page Table Entry (PTE) by selectively combining a third portion of the content of the first register with a content of the STE, while simultaneously testing the STE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the PTE with the formed address and selectively combines the content of the STE with the content of the PTE and outputs the combination as the translation buffer entry, while simultaneously testing the PTE for a Page fault.

US Patent:

48101664, Mar 7, 1989

Filed:

Aug 3, 1987

Appl. No.:

7/080791

Inventors:

Paul A. Sawizky - Norwood MA
Stephen C. Olson - Norfolk MA
Ole H. Midttun - Walpole MA

Assignee:

Bird-Johnson Company - Walpole MA

International Classification:

B63H 308
B63H 304

US Classification:

416167

Abstract:

A controllable pitch marine propeller comprises a hub body carrying a plurality of propeller blades for rotation about pivot axes disposed radially of the hub axis, a force rod extending into the hub body from the propeller shaft, and a cross-head affixed to the force rod and coupled to each propeller blade by a pin and slideway such that the propeller pitch is controlled by fore and aft movements of the force rod. The hub body has a tubular mount spigot that receives the aft end of the shaft with the shaft and mount spigot terminating aftward of the pivot axes of the blades. The cross-head is generally cup-shaped, having a base portion affixed to the force rod aftward of the pivot axes of the blades and a tubular portion extending forewardly from the base portion and surrounding aftward portions of the spigot in telescoping relation. The cross-head in supported in plain bearing relation by the hub body for fore and aft movements.

US Patent:

53773381, Dec 27, 1994

Filed:

Oct 12, 1993

Appl. No.:

8/134806

Inventors:

Stephen W. Olson - Wilmington MA
James B. MacDonald - Dracut MA
Edward D. Mann - Methuen MA
James W. Petersen - Hudson NH

Assignee:

Wang Laboratories, Inc. - Lowell MA

International Classification:

G06F 1200

US Classification:

395375

Abstract:

Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register.