Stephen C Root

US Patent:

6675374, Jan 6, 2004

Filed:

Oct 12, 1999

Appl. No.:

09/416436

Inventors:

John Samuel Pieper - Mont Vernon NH
Steven Orodon Hobbs - Westford MA
Stephen Corridon Root - Westboro MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 945

US Classification:

717141, 717131, 717142, 717154, 712235, 712237

Abstract:

A technique is provided for inserting memory prefetch instructions only at appropriate locations in program code. The instructions are inserted into the program code such that, when the code is executed, the speed and efficiency of execution of the code may be improved, cache conflicts arising from execution of the prefetch instruction may be substantially eliminated, and the number of simultaneously-executing memory prefetch operations may be limited to prevent stalling and/or overtaxing of the processor executing the code.

US Patent:

6681295, Jan 20, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/652451

Inventors:

Stephen C. Root - Westborough MA
Richard E. Kessler - Shrewsbury MA
David H. Asher - Sutton MA
Brian Lilly - Marlborough MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711128, 711133, 711134, 711136

Abstract:

A computer system has a set-associative, multi-way cache system, in which at least one way is designated as a fast lane, and remaining way(s) are designated slow lanes. Any data that needs to be loaded into cache, but is not likely to be needed again in the future, preferably is loaded into the fast lane. Data loaded into the fast lane is earmarked for immediate replacement. Data loaded into the slow lanes preferably is data that may not needed again in the near future. Slow data is kept in cache to permit it to be reused if necessary. The high-performance mechanism of data access in a modem microprocessor is with a prefetch; data is moved, with a special prefetch instruction, into cache prior to its intended use. The prefetch instruction requires less machine resources, than carrying out the same intent with an ordinary load instruction. So, the slow-lane, fast-lane decision is accomplished by having a multiplicity of prefetch instructions.

US Patent:

6911827, Jun 28, 2005

Filed:

Oct 21, 2002

Appl. No.:

10/274611

Inventors:

Isaac Kantorovich - Chestnut Hill MA, US
Christopher L. Houghton - Westborough MA, US
Stephen C. Root - Westborough MA, US
James J. St. Laurent - Oakham MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R027/28
G01R023/16

US Classification:

324615, 324 7621, 702 77

Abstract:

A method comprises generating first and second current levels and measuring the first and second current levels. The method further comprises alternately generating the first and second current levels repeatedly to generate a periodic current waveform, and measuring the voltage at at least one port in a system a plurality of times to obtain a plurality of sets of voltage measurements. The plurality of sets of voltage measurements are averaged. The method further comprises alternately generating the first and second current levels repeatedly at a predetermined number of different clock frequencies, determining a Fourier component of the averaged voltage measurements to determine clock frequency-dependent noises, removing the clock frequency-dependent noises to generate a filtered average voltage, and determining an impedance by dividing a Fourier component of the filtered average voltage by a Fourier component of the periodic current waveform having alternating first and second current levels.

US Patent:

51464217, Sep 8, 1992

Filed:

Jun 28, 1989

Appl. No.:

7/373083

Inventors:

Matthew J. Adiletta - Worcester MA
Stephen C. Root - Westboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 752

US Classification:

364758

Abstract:

The binary multiplier circuit for obtaining a product of an M-bit multiplier and an N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit. In the matrix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the column in the next most significant bit position. For every column having three or fewer original summand bits, and having the least significant column position that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most significant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any remaining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits.

US Patent:

51595680, Oct 27, 1992

Filed:

Nov 24, 1987

Appl. No.:

7/124926

Inventors:

Matthew J. Adiletta - Worcester MA
Stephen C. Root - Westboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 752

US Classification:

364758

Abstract:

The binary multiplier circuit for obtaining a product of a M-bit multiplier and a N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit. In the matrix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the column in the next most significant bit position. For every column having three or fewer original summand bits, and having the least significant column position that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most significant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any remaining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits.

US Patent:

61638218, Dec 19, 2000

Filed:

Dec 18, 1998

Appl. No.:

9/215354

Inventors:

James B. Keller - Waltham MA
Richard E. Kessler - Shrewsbury MA
Stephen C. Root - Westboro MA
Paul Geoffrey Lowney - Concord MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1320
G06F 1316
G06F 13362

US Classification:

710 57

Abstract:

A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.

US Patent:

61190756, Sep 12, 2000

Filed:

Nov 26, 1997

Appl. No.:

8/980164

Inventors:

Jeffrey Dean - Menlo Park CA
James E. Hicks - Newton MA
Stephen C. Root - Westborough MA
Carl A. Waldspurger - Atherton CA
William E. Weihl - San Francisco CA

Assignee:

Digital Equipment Corporation - Houston TX

International Classification:

G06F 900

US Classification:

702186

Abstract:

Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are randomly selected from the fetched instructions, a subset of the set of selected instructions concurrently executing with each other. A distances between the set of selected instructions is specified, and state information of the computer system is recorded while the set of selected instructions is being processed by the pipeline. The recorded state information is communicated to software where it is statistically analyzed for a plurality of sets of selected instructions to estimate statistics of the interactions among sets of selected instructions.

US Patent:

58023739, Sep 1, 1998

Filed:

Jan 29, 1996

Appl. No.:

8/592982

Inventors:

John S. Yates - Needham MA
Stephen C. Root - Westboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 945

US Classification:

395705

Abstract:

A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process. The non-native image is executed in two different enviroments with first portion executed as an interpreted image and remaining portions as a translated image.