Steve H Tsang

US Patent:

6925521, Aug 2, 2005

Filed:

Aug 28, 2002

Appl. No.:

10/229674

Inventors:

Hsiao Yi Li - Plano TX, US
Ryan G. Mueller - Plano TX, US
Steve K. Tsang - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F012/00

US Classification:

711103, 711156

Abstract:

The present invention relates to a system and a method for preventing address conflicts when establishing breakpoints and applying one or more patches to code residing on a read only memory (ROM) device. The system and method generally comprises identifying one or more program addresses which require patching, whereby one or more patch addresses are defined; evaluating address bits of the patch addresses and determining index bit positions, whereby address bits occupying the index bit positions define one or more unique tag indices; and storing the index bit positions in a tag programming memory. The system and method may furthermore comprise storing the one or more tag indices and a respectively associated one or more tag addresses in a tag control memory, forming a program index for each program address; associating each program index to a tag index; comparing the tag address associated with the tag index for each matched program index to a predetermined portion of the program address via a comparison circuit; and directing the code to patch instruction data associated with the patch address in a patch memory if the predetermined portion of the program address matches the tag address. The system and method may further comprise a RAM/ROM enable circuit operable to direct the code to the patch memory if the program address originates from the patch memory.

US Patent:

55009468, Mar 19, 1996

Filed:

Jan 27, 1995

Appl. No.:

8/380453

Inventors:

Philip Roden - Plano TX
Khodor Elnashar - Richardson TX
Brian T. Deng - Richardson TX
Steve Tsang - Dallas TX
William Saperstein - San Mateo CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1314

US Classification:

395308

Abstract:

A dual bus controller includes a system bus control module connected to a local bus control module. An optional filter is also connected to the system bus control module. A plurality of programmable status registers for the local bus is connected to the local bus control module and a time dependent reset circuit is connected to both the system bus control module and the local bus control module. The dual bus controller allows simultaneous, autonomous activity with both the local bus and the system bus via the local bus and system bus control modules. The unique interaction between the local bus and system bus control modules also allow both the local bus and system bus to interact with the dual bus controller operating as a slave without any imposed speed limitations by actively resolving bus collisions and "live-lock" conditions.