Thomas Dale Boone

US Patent:

8486289, Jul 16, 2013

Filed:

Nov 29, 2011

Appl. No.:

13/306582

Inventors:

Hamid Balamane - Portola Valley CA, US
Thomas Dudley Boone - San Jose CA, US
Jordan Asher Katine - Mountain View CA, US
Barry Cushing Stipe - San Jose CA, US

Assignee:

HGST Netherlands B.V. - Amsterdam

International Classification:

B44C 1/22
B23P 15/00

US Classification:

216 57, 216 39

Abstract:

A method of fabricating a c-aperture or E-antenna plasmonic near field source for thermal assisted recording applications in hard disk drives is disclosed. A c-aperture or E-antenna is built for recording head applications. The technique employs e-beam lithography, partial reactive ion etching and metal refill to build the c-apertures. This process strategy has the advantage over other techniques in the self-alignment of the c-aperture notch to the c-aperture internal diameter, the small number of process steps required, and the precise and consistent shape of the c-aperture notch itself.

US Patent:

20040266086, Dec 30, 2004

Filed:

Mar 5, 2004

Appl. No.:

10/795059

Inventors:

Thomas Boone - San Jose CA, US
Hironori Tsukamoto - New Haven CT, US
Jerry Woodall - New Haven CT, US

International Classification:

H01L029/76

US Classification:

438/200000

Abstract:

Novel light-emitting and/or light-responsive semiconductor devices utilize an electric field to selectively displace packets of charged carriers in an optically-active semiconductor medium. The invention, generally referred to as field aperture selecting transport or “FAST,” provides a new way to overcome the recombination-imposed speed limits associated with traditional light-emitting semiconductor devices.

US Patent:

20070247763, Oct 25, 2007

Filed:

Apr 25, 2006

Appl. No.:

11/411606

Inventors:

Thomas Boone - San Jose CA, US
Liesl Folks - Campbell CA, US
Stefan Maat - San Jose CA, US

International Classification:

G11B 5/33

US Classification:

360313000

Abstract:

An extraordinary magnetoresistive device EMR having a discontinuous shunt structure. The discontinuous shunt structure improves the linearity of response of the EMR device. The EMR device includes a EMR heterostructure that includes an EMR active layer. The heterostructure can include first, second and third semiconductor layers, with the second layer being sandwiched between the first and third layers. The middle, or second semiconductor layer provides a two dimensional electron gas. The heterostructure has first and second opposed sides, with a pair of voltage leads and a pair of current leads connected with the first side of the structure. The discontinuous shunt structure is connected with the second side of the structure and may be in the form of a series of discontinuous, electrically conductive elements, such as semi-spherical gold elements.

US Patent:

20080232001, Sep 25, 2008

Filed:

Mar 8, 2007

Appl. No.:

11/683972

Inventors:

Christian Rene Bonhote - San Jose CA, US
Thomas Dudley Boone - San Jose CA, US
Quang Le - San Jose CA, US
Jui-Lung Li - San Jose CA, US
Jeffrey S. Lille - Sunnyvale CA, US
Scott Arthur MacDonald - San Jose CA, US
Neil Leslie Robertson - Palo Alto CA, US
Xhavin Sinha - New Westminister, CA
Petrus Antonius Van Der Heijden - San Jose CA, US

International Classification:

G11B 5/33
G11B 5/127
G11B 5/147

US Classification:

360319, 360313

Abstract:

A magnetic write head for data recording having a magnetic write pole with a stepped magnetic shell structure that defines a secondary flare point. The secondary flare point defined by the magnetic shell portion can be more tightly controlled with respect to its distance from the air bearing surface (ABS) of the write head than can a traditional flare point that is photolithographically on the main pole structure. This allows the effective flare point of the write head to be moved much closer to the ABS than would otherwise be possible using currently available tooling and photolithography techniques. The write head may also include a magnetic trailing shield that wraps around the main pole portion. The trailing shield can have a hack edge defining a trailing shield throat height that is either between the secondary flare point or coincident or behind the secondary flare point, depending on design requirements

US Patent:

20220246842, Aug 4, 2022

Filed:

Apr 15, 2022

Appl. No.:

17/721369

Inventors:

- Grand Cayman, KY
Bartlomiej Adam Kardasz - Pleasanton CA, US
Jacob Anthony Hernandez - Morgan Hill CA, US
Thomas D. Boone - San Carlos CA, US
Georg Wolf - San Francisco CA, US
Mustafa Pinarbasi - Morgan Hill CA, US

International Classification:

H01L 43/12
H01L 27/22
H01L 43/02
H01L 43/10
G11C 11/16
H01F 41/32
H01F 10/32

Abstract:

A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

US Patent:

20200350493, Nov 5, 2020

Filed:

May 1, 2019

Appl. No.:

16/400204

Inventors:

- Fremont CA, US
Pradeep Manandhar - Fremont CA, US
Jorge Vasquez - San Jose CA, US
Bartlomiej Adam Kardasz - Pleasanton CA, US
Thomas D. Boone - San Carlos CA, US

International Classification:

H01L 43/12
H01L 27/22
G11C 11/16

Abstract:

A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transfer the image of the Ru hard mask onto the underlying memory element layers. A high-angle ion milling an be performed to remove any redeposited material from the sides of the memory element layers, and a non-magnetic, dielectric material can be deposited. A thermal annealing process can then be performed to repair any damage caused by the previously performed ion milling processes.

US Patent:

20200343043, Oct 29, 2020

Filed:

Apr 29, 2019

Appl. No.:

16/397987

Inventors:

- Fremont CA, US
Pradeep Manandhar - Fremont CA, US
Thomas D. Boone - San Carlos CA, US

International Classification:

H01F 41/34
H01L 43/12
G11C 11/16
H01L 43/02
H01F 10/32
H01L 27/22

Abstract:

A method for manufacturing a magnetic memory element structure using a Ru hard mask and a self-aligned pillar formation process. A plurality of magnetic memory element layers are deposited over a substrate, including a magnetic reference layer, a non-magnetic barrier layer deposited over the magnetic reference layer, a magnetic free layer deposited over the non-magnetic barrier layer and a Ru hard mask layer deposited over the Ru hard mask layer. A mask structure is formed over the Ru hard mask and the image of the mask structure is transferred to the Ru hard mask. A first ion milling is performed to transfer the image of the patterned Ru hard mask onto the underlying magnetic free layer and non-magnetic barrier layer, the first ion milling being terminated when the magnetic reference layer has been reached. A non-magnetic dielectric protective layer is then deposited and a second ion milling is performed.

US Patent:

20200243757, Jul 30, 2020

Filed:

Jan 28, 2019

Appl. No.:

16/259791

Inventors:

- Fremont CA, US
Bartlomiej Adam Kardasz - Pleasanton CA, US
Jacob Anthony Hernandez - Morgan Hill CA, US
Thomas D. Boone - San Carlos CA, US
Georg Wolf - San Francisco CA, US
Mustafa Pinarbasi - Morgan Hill CA, US

International Classification:

H01L 43/12
H01L 27/22
H01L 43/02
H01L 43/10
H01F 10/32
H01F 41/32
G11C 11/16

Abstract:

A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.