Thomas F Preston

US Patent:

50560417, Oct 8, 1991

Filed:

Jul 31, 1989

Appl. No.:

7/387404

Inventors:

Karl M. Guttag - Missouri City TX
Michael Asal - Sugar Land TX
Richard Simpson - Bedford, GB2
Thomas Preston - Middlebury CT
John Sharkey - Glasgow, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1520

US Classification:

364518

Abstract:

A graphics processor device is disclosed which performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus. The bit-by-bit masking may also be done for data in internal memory, by multiplexing the CPU data and the internal memory data onto the CPU data bus.

US Patent:

RE348813, Mar 21, 1995

Filed:

Jun 21, 1990

Appl. No.:

7/541879

Inventors:

Karl M. Guttag - Missouri City TX
Michael D. Asal - Sugar Land TX
Thomas Preston - Middlebury CT

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1520

US Classification:

345133

Abstract:

A graphics data processing apparatus having graphic image operations on two images. Two graphic images are formed into a single combined image based upon a predetermined combination of the multibit color codes representing corresponding pixels of the two images. A transparent color code is permitted for the first of the graphic images. The combination of a transparent color code from the first graphic image with any color code from the second graphic image yields the color code of the second graphic image. This innovation enables the use of color codes having selectable numbers of bits set by the number stored in a pixel size register. In particular the transparent color code, which is detected by a transparent color code detection device independent of the image operation, has a selectable number of bits set by the pixel size register in a manner like any other color code. This enables the same graphics data processing apparatus to be applicable to a wide variety of applications having images using differing lengths of color codes while preserving the transparency function.

US Patent:

51858592, Feb 9, 1993

Filed:

Aug 15, 1991

Appl. No.:

7/745642

Inventors:

Karl M. Guttag - Missouri City TX
Michael Asal - Sugar Land TX
Richard Simpson - Bedford, GB2
Thomas Preston - Middlebury CT
John Sharkey - Glasgow, GB

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1520

US Classification:

395164

Abstract:

A graphics processor device performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus. The bit-by-bit masking may also be done for data in internal memory, by multiplexing the CPU data and the internal memory data onto the CPU data bus.