Timothy P Dunham

US Patent:

6559543, May 6, 2003

Filed:

Nov 16, 2001

Appl. No.:

09/991769

Inventors:

Timothy G. Dunham - South Burlington VT
Howard S. Landis - Underhill VT
William T. Motsiff - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257758, 438622

Abstract:

Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

US Patent:

6743710, Jun 1, 2004

Filed:

Jan 15, 2003

Appl. No.:

10/345441

Inventors:

Timothy G. Dunham - South Burlington VT
Howard S. Landis - Underhill VT
William T. Motsiff - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 214763

US Classification:

438622, 438687, 438652, 438653

Abstract:

Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

US Patent:

6992002, Jan 31, 2006

Filed:

Nov 26, 2002

Appl. No.:

10/305644

Inventors:

Timothy G. Dunham - South Burlington VT, US
Ezra D. B. Hall - Colchester VT, US
Howard S. Landis - Underhill VT, US
Mark A. Lavin - Katonah NY, US
William C. Leipold - Enosburg Falls VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438622, 438631, 438633, 438637

Abstract:

An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.

US Patent:

7051307, May 23, 2006

Filed:

Dec 3, 2003

Appl. No.:

10/707286

Inventors:

Gary S. Ditlow - Garrison NY, US
Daria R. Dooling - Huntington VT, US
Timothy G. Dunham - South Burlington VT, US
William C. Leipold - Enosburg Falls VT, US
Stephen D. Thomas - Essex Junction VT, US
Ralph J. Williams - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 7

Abstract:

Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

US Patent:

7289658, Oct 30, 2007

Filed:

Jun 24, 2003

Appl. No.:

10/604063

Inventors:

Joseph B. Allen - Wappingers Falls NY, US
Timothy G. Dunham - South Burlington VT, US
Valarmathi C. Shanmugam - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06K 9/00

US Classification:

382144

Abstract:

A method for reducing a number of shapes, and a computer readable program code adapted to perform said method. The method forms first and second shape patterns. The second shape pattern includes the first shape pattern and error shapes. The error shapes are extracted from the second shape pattern. At least one environment shape corresponding to each error shape is derived from a subset of the error shapes. For example, each error shape in the subset may be expanded to form a corresponding expanded shape, and at least one environment shape corresponding to each expanded shape may be formed by removing all portions of the expanded shape common to the second shape pattern. The environment shape reflects a local geometric environment of its corresponding error shape. A subset of the environment shapes are deleted such that only unique environment shapes satisfying a selection criterion remain.

US Patent:

7312141, Dec 25, 2007

Filed:

Oct 21, 2005

Appl. No.:

11/256025

Inventors:

Timothy G. Dunham - South Burlington VT, US
Ezra D. B. Hall - Richmond VT, US
Howard S. Landis - Underhill VT, US
Mark A. Lavin - Katonah NY, US
William C. Leipold - Enosburg Falls VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438597, 257E21575

Abstract:

An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

US Patent:

7353472, Apr 1, 2008

Filed:

Aug 12, 2005

Appl. No.:

11/202591

Inventors:

David L. DeMaris - Austin TX, US
Timothy G. Dunham - South Burlington VT, US
William C. Leipold - Enosburg Falls VT, US
Daniel N. Maynard - Craftsbury Common VT, US
Michael E. Scaman - Goshen NY, US
Shi Zhong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 7

Abstract:

A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

US Patent:

7498250, Mar 3, 2009

Filed:

Aug 13, 2007

Appl. No.:

11/837768

Inventors:

Timothy G. Dunham - South Burlington VT, US
Ezra D. B. Hall - Richmond VT, US
Howard S. Landis - Underhill VT, US
Mark A. Lavin - Katonah NY, US
William C. Leipold - Enosburg Falls VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438597, 257E21575

Abstract:

An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.