Wai Han Fong

US Patent:

6404839, Jun 11, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/797033

Inventors:

Wai Fong - San Jose CA
Jyh-Ming Jong - Saratoga CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H03K 2100

US Classification:

377 47, 377 48, 377 80, 377 8, 327115, 327175

Abstract:

A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e. g. 2.

US Patent:

6880118, Apr 12, 2005

Filed:

Oct 25, 2001

Appl. No.:

09/999877

Inventors:

Cecilia T. Chen - Alameda CA, US
Jyh-Ming Jong - Saratoga CA, US
Wai Fong - San Jose CA, US
Leo Yuan - Los Altos CA, US
Brian L. Smith - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R031/28

US Classification:

714727, 714729

Abstract:

A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

US Patent:

6937680, Aug 30, 2005

Filed:

Apr 24, 2001

Appl. No.:

09/842332

Inventors:

Wai Fong - San Jose CA, US
Jyh-Ming Jong - Saratoga CA, US
Leo Yuan - Los Altos CA, US
Brian Smith - Sunnyvale CA, US
Prabhansu Chakrabarti - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L007/00

US Classification:

375357, 370503, 327142, 714 23, 714 55, 713400, 713500, 713601, 709228

Abstract:

A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal. The resetting of the source synchronous receiver may be performed locally, and does not reset the core logic of the device in which it is implemented, nor any other source synchronous port on the device. Thus, other source synchronous ports on the device, as well as the core logic, may be able to continue operations as normal.

US Patent:

6944692, Sep 13, 2005

Filed:

Sep 13, 2001

Appl. No.:

09/951928

Inventors:

Brian L. Smith - Sunnyvale CA, US
Jue Wu - Mountain View CA, US
Jyh-Ming Jong - Saratoga CA, US
Wai Fong - San Jose CA, US
Leo Yuan - Los Altos CA, US
Prabhansu Chakrabarti - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F013/42
G06F011/04
G06K005/04

US Classification:

710106, 714700, 713503

Abstract:

A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

US Patent:

7296104, Nov 13, 2007

Filed:

Sep 12, 2005

Appl. No.:

11/224277

Inventors:

Brian L. Smith - Sunnyvale CA, US
Jue Wu - Mountain View CA, US
Jyh-Ming Jong - Saratoga CA, US
Wai Fong - San Jose CA, US
Leo Yuan - Los Altos CA, US
Prabhansu Chakrabarti - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 13/42
G06F 11/04
G06K 5/04

US Classification:

710106, 714700, 713503

Abstract:

A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

US Patent:

20190058627, Feb 21, 2019

Filed:

Aug 16, 2017

Appl. No.:

15/678969

Inventors:

- Schenectady NY, US
Wai Loon Fong - Livermore CA, US
Karel Barnoski - Dublin CA, US
Peter Ingulli - San Ramon CA, US

International Classification:

H04L 12/24
G06F 17/30
H04W 4/00
H04L 29/08

Abstract:

Systems and methods for filtering a large group of devices are presented. In an example embodiment, a value is accessed for each of a plurality of attributes for each of a plurality of devices. Also accessed is a filter set including one or more filters. Each of the filters comprises one of the attributes, a filter value, and a relational operator relating the attribute to the filter value. The attribute of at least one of the filters indicates an event applicable to individual devices, and a corresponding filter value indicates whether to filter the devices based on the presence or absence of a previous occurrence of the event. The filter set is compared to the attributes of each of the devices to identify those of the devices that satisfy all of the filters of the filter set. A representation of at least some of the identified devices is displayed.