Walter R Allen

US Patent:

7949851, May 24, 2011

Filed:

Dec 28, 2007

Appl. No.:

11/966919

Inventors:

Walter Allen - Austin TX, US
Sunil Atri - Austin TX, US
Robert France - Austin TX, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711203, 711202, 711E12058

Abstract:

Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.

US Patent:

8239611, Aug 7, 2012

Filed:

Dec 28, 2007

Appl. No.:

11/966923

Inventors:

Walter Allen - Austin TX, US
Robert France - Austin TX, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711103, 711165

Abstract:

Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

US Patent:

20090164750, Jun 25, 2009

Filed:

Dec 21, 2007

Appl. No.:

11/963200

Inventors:

Sunil Atri - Austin TX, US
Robert Brent France - Austin TX, US
Walter Allen - Wellington CO, US

Assignee:

SPANSION LLC - Sunnyvale CA

International Classification:

G06F 12/00

US Classification:

711209, 711E12001

Abstract:

A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data.