Wei Hsuan Lu

US Patent:

6519688, Feb 11, 2003

Filed:

Sep 29, 2000

Appl. No.:

09/676460

Inventors:

Wei G. Lu - San Jose CA
Biranchi N. Nayak - San Jose CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711167

Abstract:

In a synchronized memory system comprising a memory controller externally coupled to a synchronous memory, a read valid loop back signal is introduced for the memory controller to track the delays of signals exchanged between the memory controller and the synchronous memory, so that the uncertainty introduced by I/O pads and PCB traces used to facilitate the coupling of the memory controller with the sychronous memory is no longer the limiting factor for the speed of the memory controller. An asynchronous FIFO buffer is used to latch read data returned by the synchronous memory based on the read valid loop back signal.

US Patent:

6983319, Jan 3, 2006

Filed:

Apr 6, 2001

Appl. No.:

09/827742

Inventors:

Wei Lu - Coppell TX, US
Junan Duan - Lewisville TX, US

Assignee:

Permeo Technologies, Inc. - Irving TX

International Classification:

G06F 15/173

US Classification:

709223, 709227, 370389, 370392

Abstract:

A method and system is disclosed for dynamically managing port and network addresses for a private network using at least one dynamic port management (DPM) driver and a DPM server. The DPM driver is installed on a computer of the private network and the DPM server is installed on a gateway module of the private network. The private network uses a plurality of unregistered network address for its internal uses and has one or more registered network address for communicating with computers outside of the private network. When initiating an application session communicating with at least one computer outside of the private network, a first port is obtained from the DPM driver. A setup process is established for exchanging information between the DPM driver and the DPM server in order to reserve a registered network address and, if the first port is replaceable, for dynamically assigning a second port. The reserved registered network address and the dynamically assigned second port are used for completing communications of the application session.

US Patent:

7031327, Apr 18, 2006

Filed:

Aug 24, 2001

Appl. No.:

09/939147

Inventors:

Wei Lu - Coppell TX, US

Assignee:

Permeo Technologies, Inc. - Irving TX

International Classification:

H04L 12/28
H04L 12/56
G06F 15/16

US Classification:

370401, 709245

Abstract:

A method and system is disclosed for controlling packet communications between a first computer network and a second computer network. A driver module implemented in a first computer extracts information about an application session and a network address and port used by the first computer for sending packets of the application session to a second computer in the second computer network when the first computer initially determining a port for the application session. The driver module sends the extracted information to a gateway node of the first computer network, the gateway node being implemented with a server module and the gateway node monitoring one or more packets exchanging between the first and second computer networks. A look-up table is then established for recording the relation between the application and the network address and port used by the first computer for the application. The packet communications between the first and second networks are thus controlled by the gateway node based on the established look-up table.

US Patent:

7142823, Nov 28, 2006

Filed:

Jan 29, 2004

Appl. No.:

10/769205

Inventors:

John D. Logue - Placerville CA, US
Austin H. Lesea - Los Gatos CA, US
Wei Lu - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04B 1/40

US Classification:

455 76, 455 75, 455 831, 455260, 375371, 375374, 375376

Abstract:

A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein a rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates an error value based on the snapshots. The tapped delay line module produces the output clock based on the error value.

US Patent:

7283838, Oct 16, 2007

Filed:

Apr 22, 2005

Appl. No.:

10/907951

Inventors:

Wei Lu - Cupertino CA, US

International Classification:

H04M 1/00

US Classification:

4555501, 455418, 455419, 370469, 370474, 709224

Abstract:

An open baseband processing architecture for next generation wireless and mobile communication terminal system supporting full integration and convergence of existing and future wireless standards with open processing engines to optimize the terminal system performance and network resource management.

US Patent:

7391246, Jun 24, 2008

Filed:

Mar 2, 2004

Appl. No.:

10/792055

Inventors:

Wei Guang Lu - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03L 7/00

US Classification:

327161, 327153

Abstract:

A digital high speed programmable delayed locked loop (DLL) includes a zero degree phase shift digital delay line, at least one intermediate phase shift digital delay line, a three hundred and sixty degree phase shift digital delay line, and a digital control module. The zero degree phase shift, intermediate phase shift, and 360 degree phase shift digital delay lines are operably coupled to produce, from a clock signal, zero phase shifted, intermediate phase shifted, and 360 phase shifted representations, respectively, of the clock signal. The digital control module is operably coupled to produce an intermediate control signal for the intermediate phase shift digital delay line and a 360 degree control signal for the 360 degree phase shift digital delay line based on a phase difference between the zero phase shifted representation of the clock signal and the three hundred and sixty degree phase shifted representation of the clock signal.

US Patent:

7463622, Dec 9, 2008

Filed:

Nov 10, 2004

Appl. No.:

10/904422

Inventors:

Wei Lu - Cupertino CA, US
Jianhong Hu - Cupertino CA, US

International Classification:

H04Q 7/22
H04L 12/56
H04L 12/50

US Classification:

370352, 370328, 370338, 370401, 455445, 455433

Abstract:

An advanced communication terminal system of integrating mobile communications, wireless access systems and wireline communications into one open architecture platform supporting cost-effective broadband services in both wireless and wired communication environment with one integrated terminal device in order to maximize the wireless spectrum utilization and optimize the network resource management.

US Patent:

7518396, Apr 14, 2009

Filed:

Jun 25, 2007

Appl. No.:

11/823057

Inventors:

Venu M. Kondapalli - Sunnyvale CA, US
Wei Guang Lu - San Jose CA, US
P. Hugo Lamarche - Campbell CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38
H03K 19/173
H03K 17/693

US Classification:

326 38, 716 16

Abstract:

A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.