William Graham Shepherd

US Patent:

6528351, Mar 4, 2003

Filed:

Sep 24, 2001

Appl. No.:

09/963337

Inventors:

Richard J. Nathan - Morgan Hill CA
William H. Shepherd - Placitas NM

Assignee:

JigSaw tek, Inc. - Gilroy CA

International Classification:

H01L 2144

US Classification:

438118, 438124, 438126, 438127

Abstract:

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chips.

US Patent:

20030057544, Mar 27, 2003

Filed:

Mar 12, 2002

Appl. No.:

10/097363

Inventors:

Richard Nathan - Morgan Hill CA, US
William Shepherd - Placitas NM, US

International Classification:

H01L021/48
H01L023/48
H01L029/40

US Classification:

257/700000, 257/692000, 257/778000, 438/108000, 257/782000, 257/786000, 438/612000, 438/618000

Abstract:

A monolithic integrated structure including one or more packaged components such as integrated circuits, discreet components, LED's, photocouplers and the like is formed by placing electrically conductive lands on one surface of each packaged component, and then placing one or more packaged components into a substrate such that the surface of each packaged component containing the electrically conductive lands is visible and substantially coplanar with the top surface of the substrate. An electrically conductive layer is then formed over the top surface of the substrate, on the visible surfaces of each of the packaged components and on the electrically conductive lands contained thereon. The electrically conductive layer is then patterned using standard photolithographic techniques known in the semiconductor and printed circuit processing arts to form an electrical interconnect which connects the packaged components into a desired electrical circuit. The resulting structure thus is low cost yielding either packaged single integrated circuit structures or multi-package structures which either form an electronic system or which are capable of being electrically interconnected with other such structures to form an entire electronic system.

US Patent:

20030059976, Mar 27, 2003

Filed:

Mar 12, 2002

Appl. No.:

10/098021

Inventors:

Richard Nathan - Morgan Hill CA, US
William Shepherd - Placitas NM, US

International Classification:

H01L021/48

US Classification:

438/106000

Abstract:

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chip. A plurality of substrates with embedded integrated circuit chips can be stacked to form a composite multichip, multi-layered structure. Additional chips, packaged or unpackaged, can be placed on the top of this composite structure.

US Patent:

20030102572, Jun 5, 2003

Filed:

Sep 13, 2001

Appl. No.:

09/953005

Inventors:

Richard Nathan - Morgan Hill CA, US
William Shepherd - Placitas NM, US

International Classification:

H01L023/48
H01L023/52
H01L029/40

US Classification:

257/780000

Abstract:

A monolithic integrated structure including one or more packaged components such as integrated circuits, discreet components, LED's, photocouplers and the like is formed by placing electrically conductive lands on one surface of each packaged component, and then placing one or more packaged components into a substrate such that the surface of each packaged component containing the electrically conductive lands is visible and substantially coplanar with the top surface of the substrate. An electrically conductive layer is then formed over the top surface of the substrate, on the visible surfaces of each of the packaged components and on the electrically conductive lands contained thereon. The electrically conductive layer is then patterned using standard photolithographic techniques known in the semiconductor and printed circuit processing arts to form an electrical interconnect which connects the packaged components into a desired electrical circuit. The resulting structure thus is low cost yielding either packaged single integrated circuit structures or multi-package structures which either form an electronic system or which are capable of being electrically interconnected with other such structures to form an entire electronic system.