Yan Dr Li

US Patent:

20130121072, May 16, 2013

Filed:

Jan 7, 2013

Appl. No.:

13/735878

Inventors:

SanDisk Technologies, Inc. - Plano TX, US
Yan Li - Milpitas CA, US

Assignee:

SanDisk Technologies, Inc. - Plano TX

International Classification:

G11C 16/26
G11C 16/04

US Classification:

36518503, 36518518

Abstract:

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.