Yong Vincent Jiang

US Patent:

6920552, Jul 19, 2005

Filed:

Feb 27, 2002

Appl. No.:

10/083291

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G03F007/38

US Classification:

713 1

Abstract:

A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e. g. , from internal device logic) is output from the data I/O device to the at least one port.

US Patent:

6934866, Aug 23, 2005

Filed:

Mar 18, 2002

Appl. No.:

10/098337

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporaton - Irvine CA

International Classification:

G06F001/12

US Classification:

713401

Abstract:

A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

US Patent:

7024576, Apr 4, 2006

Filed:

Jul 14, 2005

Appl. No.:

11/180628

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G04F 8/00

US Classification:

713400

Abstract:

A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

US Patent:

7134010, Nov 7, 2006

Filed:

Jun 10, 2005

Appl. No.:

11/149182

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G03F 7/38

US Classification:

713 1

Abstract:

A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e. g. , from internal device logic) is output from the data I/O device to the at least one port.

US Patent:

7308568, Dec 11, 2007

Filed:

Oct 16, 2006

Appl. No.:

11/580956

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G03F 7/38

US Classification:

713 1

Abstract:

A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e. g. , from internal device logic) is output from the data I/O device to the at least one port.

US Patent:

7348820, Mar 25, 2008

Filed:

Aug 29, 2006

Appl. No.:

11/511309

Inventors:

Yong H. Jiang - Fremont CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 7/06

US Classification:

327158, 327149

Abstract:

A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances, producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances, utilizing the correction signal to change a delay setting and forwarding the correction signal to slave DLL modules in communication with the DLL module. The comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced.

US Patent:

7904625, Mar 8, 2011

Filed:

Nov 12, 2008

Appl. No.:

12/269212

Inventors:

Yong Jiang - San Jose CA, US
Zhenyu Zhang - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 13/10
G06F 13/38

US Classification:

710110, 710100, 710104

Abstract:

An apparatus includes a Universal Serial Bus (USB) transceiver of a USB host controller, a first pull-down resistor, a first switch, a second pull-down resistor, a second switch, and a detachment module. The USB transceiver has a differential output. The first switch electrically couples the first pull-down resistor to a positive terminal of the differential output in response to a first switch control signal. The second switch electrically couples the second pull-down resistor to a negative terminal of the differential output in response to a second switch control signal. The detachment module selectively determines whether a USB device is electrically coupled to the differential output by checking a voltage at the differential output while at least one of the first switch control signal or the second switch control signal is asserted. The detachment module determines whether the USB device is electrically coupled to the differential output by checking the positive terminal when the USB transceiver is in a full-speed idle state and by checking the negative terminal when the USB transceiver is in a low-speed idle state.

US Patent:

8321706, Nov 27, 2012

Filed:

Jul 23, 2008

Appl. No.:

12/178268

Inventors:

Zhenyu Zhang - Campbell CA, US
James Kang-Wuu Jan - San Jose CA, US
Frank Huang - Pleasanton CA, US
Yong Jiang - San Jose CA, US
Yui Lin - Cupertino CA, US
Kevin Lo - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

G06F 1/26

US Classification:

713323, 713324

Abstract:

USB self-idling techniques are described. In one or more embodiments, a Universal Serial Bus (USB) device comprises one or more modules to communicate via USB and self-idle by presenting an idle mode to a USB host and entering a suspend mode while the USB host is presented with the idle mode.