Yuyun Y Liao

US Patent:

7035331, Apr 25, 2006

Filed:

Feb 20, 2002

Appl. No.:

10/081926

Inventors:

Yuyun Liao - Chandler AZ, US
Nigel C. Paver - Austin TX, US
James E. Quinlan - Marlboro MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 7/12
H04N 11/02

US Classification:

37524001, 37524021, 345643

Abstract:

In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a STMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into a sum and a carry vector. The two least significant bits of the sum vector and the LSB of the carry vector are dropped before being input to the 36-bit SIMD adder. The two resultant 8-bit vectors are added by the 36-bit adder to directly generate the average pixel value result.

US Patent:

7107305, Sep 12, 2006

Filed:

Oct 5, 2001

Appl. No.:

09/972720

Inventors:

Deli Deng - Austin TX, US
Anthony Jebson - Austin TX, US
Yuyun Liao - Chandler AZ, US
Nigel C. Paver - Austin TX, US
Steve J. Strazdus - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38

US Classification:

708523, 708233

Abstract:

A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit×32-bit operations.

US Patent:

20030172101, Sep 11, 2003

Filed:

Apr 4, 2003

Appl. No.:

10/407048

Inventors:

Yuyun Liao - Chandler AZ, US
Tom Hameenanttila - Phoenix AZ, US
David Roberts - Gilbert AZ, US

International Classification:

G06F007/38

US Classification:

708/523000

Abstract:

A multiply-accumulate unit, or MAC, may achieve high throughput. The MAC need not use redundant hardware, such as multiple Wallace trees, or pipelining logic, yet may perform Wallace tree and carry look-ahead adder functions simultaneously for different operations.

US Patent:

6434587, Aug 13, 2002

Filed:

Jun 14, 1999

Appl. No.:

09/333153

Inventors:

Yuyun Liao - Chandler AZ
David Roberts - Gilbert AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 752

US Classification:

708629, 708628

Abstract:

An embodiment of the present invention is a mixed length encoding unit. The mixed length may be a 12/16 bits (12/16-b) encoding algorithm within a multiply-accumulate (MAC). The mixed length encoding unit includes 16-b Booth encoder adapted to produce eight partial product vectors from sixteen bits of data. The 16-b Booth encoder is coupled to a four stage Wallace Tree. During a first cycle of the invention, a multiplex system directs the eight partial products and an accumulation vector to a four stage Wallace Tree. During subsequent cycles, the multiplex system directs six partial product vectors, an accumulation vector, one carry-feedback input vector, and one sum-feedback input vector to the four stage Wallace Tree.