Adrian R Salinas

US Patent:

8028709, Oct 4, 2011

Filed:

Jan 12, 2009

Appl. No.:

12/351987

Inventors:

Adrian Salinas - Garland TX, US
Joel Peterson - Pottsboro TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B08B 3/04
B08B 3/00
B08B 3/12
B08B 6/00
B05C 11/00
B05C 13/00
B05C 13/02

US Classification:

1341041, 134199, 118 70

Abstract:

A cleaning system which can be integrated into a coater track system for use in the production of semiconductor devices and methods for its use are provided. The cleaning system can include a series of nozzles having assorted configurations and features which provide uniform and efficient rinsing of excess material.

US Patent:

20060099829, May 11, 2006

Filed:

Nov 5, 2004

Appl. No.:

10/981880

Inventors:

Paul Andres - Dallas TX, US
Adrian Salinas - Garland TX, US

International Classification:

H01L 21/31

US Classification:

438782000

Abstract:

A method of forming a layer of photoresist over a surface of a semiconductor wafer by forming a layer of pre-wet solvent over the surface and forming the layer of photoresist over the layer of pre-wet solvent . Also, a layer of photoresist formed by this method.

US Patent:

20200058485, Feb 20, 2020

Filed:

Aug 16, 2019

Appl. No.:

16/542628

Inventors:

- Dallas TX, US
Adrian Salinas - Garland TX, US
Elizabeth C. Stewart - Dallas TX, US
Dhanoop Varghese - Plano TX, US
Thomas D. Bonifield - Dallas TX, US

International Classification:

H01L 21/02
H01L 49/02

Abstract:

An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.