Alejandro G Gonzalez

US Patent:

7555668, Jun 30, 2009

Filed:

Jul 18, 2006

Appl. No.:

11/488494

Inventors:

Paul Joseph Murtagh - Duluth GA, US
Prashant Shamarao - Alpharetta GA, US
Alejandro Flavio Gonzalez - Alpharetta GA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

G06F 1/04

US Classification:

713503, 713401, 713500

Abstract:

A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.

US Patent:

8513992, Aug 20, 2013

Filed:

Sep 10, 2010

Appl. No.:

12/879995

Inventors:

Amit Majumder - Duluth GA, US
Praveen Rajan Singh - Duluth GA, US
Alejandro Flavio Gonzalez - Alpharetta GA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

H03L 7/06

US Classification:

327157, 327148

Abstract:

A method and apparatus for implementation of PLL minimum frequency via voltage comparison have been described.

US Patent:

20190013054, Jan 10, 2019

Filed:

Jul 24, 2018

Appl. No.:

16/043694

Inventors:

- San Jose CA, US
Alejandro F. Gonzalez - Johns Creek GA, US

International Classification:

G11C 7/22
G11C 5/04
G11C 7/12
G06F 13/40
G11C 7/10

Abstract:

An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.

US Patent:

20170287538, Oct 5, 2017

Filed:

Apr 5, 2016

Appl. No.:

15/090818

Inventors:

- San Jose CA, US
Alejandro F. Gonzalez - Johns Creek GA, US

International Classification:

G11C 7/22
G11C 7/12

Abstract:

An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.