Ana Ley Ley

US Patent:

6576404, Jun 10, 2003

Filed:

Dec 19, 2000

Appl. No.:

09/741568

Inventors:

John Hu - Sunnyvale CA
Ana Ley - Sunnyvale CA
Philippe Schoenborn - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G03C 500

US Classification:

430317, 430318, 430313, 430 5

Abstract:

A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.

US Patent:

6846569, Jan 25, 2005

Filed:

Apr 2, 2003

Appl. No.:

10/405666

Inventors:

John Hu - Sunnyvale CA, US
Ana Ley - Sunnyvale CA, US
Philippe Schoenborn - San Jose CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

B32B 1500

US Classification:

428450, 428446, 430 5

Abstract:

A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.

US Patent:

57364184, Apr 7, 1998

Filed:

Jun 7, 1996

Appl. No.:

8/659860

Inventors:

Nicholas F. Pasch - Pacifica CA
Ana Ley - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2186

US Classification:

437 41

Abstract:

According to the present invention, there is provided a method for fabricating a field effect transistor having reduced hot electron effects. In one embodiment, the method comprises the steps of disposing a gate oxide layer on a semiconductor substrate; disposing a gate material on the gate oxide layer; masking a portion of the gate material; anisotropically etching a gate structure into the gate material such that a trench is formed in the semiconductor substrate; implanting a source structure in the semiconductor substrate, the source structure having a first doping region superjacent a second doping region, the second doping region being lightly doped relative to the first doping region.