Brett Andrew Walker

US Patent:

6711391, Mar 23, 2004

Filed:

Oct 10, 2000

Appl. No.:

09/686265

Inventors:

Brett C. Walker - San Diego CA
Eric Zeisel - San Diego CA
Gurkanwal S. Sahota - San Diego CA

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

H04B 106

US Classification:

4552341, 4551273

Abstract:

Techniques to linearly (in dB) adjust the gains of variable gain elements (i. e. , variable gain amplifiers or VGAs) in a receiver or transmitter. An input control signal is provided to a conditioning circuit that conditions the control signal to achieve various signal characteristics. The input control signal is limited to within a particular range of values, temperature compensated, scaled (or normalized) to the supply voltages, shifted with an offset, or manipulated in other fashions. The conditioned signal is then provided to an input stage of a linearizer that generates a set of exponentially related signals. This is achieved using, for example, a differential amplifier in which the conditioned control signal is applied to the inputs of the differential amplifier and the collector currents from the differential amplifier comprises the exponentially related signals. An output stage within the linearizer receives the exponentially related signals and, in response, generates a gain control signal. By approximately matching the output stage to a gain stage of the variable gain element and by using the gain control signal generated by output stage, the gain transfer function of the VGA approximates that of the exponentially related signals.

US Patent:

6845083, Jan 18, 2005

Filed:

Feb 3, 2003

Appl. No.:

10/357739

Inventors:

Steven M. Mollenkopf - San Diego CA, US
Puay Hoe Andrew See - San Deigo CA, US
Brett C. Walker - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04L 1500

US Classification:

370215, 370252, 455112, 4551142, 455216

Abstract:

A transmitter converts a digital baseband signal input for transmission by an antenna to support multiple communication standards. An over-deviation phase multiplier increases signal phase deviation by a factor of M. A digital phase modulator applies trigonometric lookup tables. A digital intermediate frequency up-converter up-shifts frequencies of desired signal content. First and second digital-to-analog converters (DACs) and use relatively low-bit operations, which add DAC noise. First and second low pass filters and apply rejection above frequencies of desired signal content. An analog I/Q modulator converts from complex to real signals, adding an unwanted signal spaced from the desired signal content by an intermediate frequency multiple. A limiter reduces amplitude modulated noise. An over-deviation phase divider divides signal phase deviation by 1/M to reduce phase modulated noise.

US Patent:

6882185, Apr 19, 2005

Filed:

Jul 2, 1998

Appl. No.:

09/109504

Inventors:

Brett Christopher Walker - San Diego CA, US
Peter C. Gazzerro - San Diego CA, US

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

H03F003/45

US Classification:

327103, 327346, 327 67

Abstract:

An apparatus and method of generating a current pair I, Iwhere the ratio of the pair is exponentially related to a control signal, and where either Ior Iis greater than or less than a minimum or maximum value includes a feedback correction circuit used to sense the value of Ior I. The correction circuit supplies a boost current Iwhen the sensed value of Ior Iis less than or greater than the minimum or maximum value. Iis preferably maintained proportional to the difference of the desired value and Ior I.

US Patent:

6888913, May 3, 2005

Filed:

Jul 2, 2002

Appl. No.:

10/189036

Inventors:

Brett C. Walker - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H03K021/00

US Classification:

377 47, 377 48

Abstract:

A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting stages are used to generate the first and second modulus control signals. The first modulus control signal is at a first logic level when the associated counter is at a non-zero value and is at a second logic level when the associated counter reaches zero. The second modulus control signal is generated by a second counter and has a first logic value when the second counter is in a non-zero state and a second logic value when the second counter reaches zero.

US Patent:

6906592, Jun 14, 2005

Filed:

Nov 3, 2003

Appl. No.:

10/700860

Inventors:

Kenneth Barnett - Oceanside CA, US
Brett C. Walker - San Diego CA, US
Kevin Gard - Raleigh NC, US

Assignee:

Qualcomm Inc - San Diego CA

International Classification:

H03G003/20

US Classification:

330289, 330283

Abstract:

A radio frequency (RF) driver amplifier system and method that provides linear in decibel gain control is provided. The RF driver amplifier system comprises a linear transconductor receiving an input voltage and providing a controlled current based on input voltage received, temperature compensation circuitry for varying current from the linear transconductor according to absolute temperature, an exponential current controller receiving current varied according to temperature and providing an exponential current in response, and an inductive degeneration compensator receiving exponential current and providing a control current to driver amplifier circuitry, thereby compensating for inductive degeneration due to at least one inductor in the driver amplifier circuitry. Control current passes from the inductive degeneration compensator to the driver amplifier circuitry. Output gain from the driver amplifier circuitry varies linearly in decibels with respect to the input voltage.

US Patent:

7062229, Jun 13, 2006

Filed:

Mar 6, 2002

Appl. No.:

10/092868

Inventors:

Jeremy D. Dunworth - Cardiff CA, US
Brett C. Walker - San Diego CA, US

International Classification:

H04B 1/40

US Classification:

455 76, 455 75, 455260

Abstract:

In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more amplitude calibration techniques prior to enabling the PLL. For example, an amplitude calibration unit may be used to selectively activate switched unit current sources within a tail current source of the VCO. In this manner, the amplitude the signal generated by the oscillator can be adjusted without requiring closed-loop amplitude monitoring or control.

US Patent:

7076225, Jul 11, 2006

Filed:

Dec 21, 2001

Appl. No.:

10/034734

Inventors:

Tao Li - San Diego CA, US
Christian Holenstein - San Diego CA, US
Inyup Kang - San Diego CA, US
Brett C. Walker - San Diego CA, US
Paul E. Peterzell - San Diego CA, US
Raghu Challa - San Diego CA, US
Matthew L. Severson - Oceanside CA, US
Arun Raghupathy - San Diego CA, US
Gilbert Christopher Sih - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04B 7/00

US Classification:

4552451, 4552321, 455296, 375344, 375346

Abstract:

A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

US Patent:

7106138, Sep 12, 2006

Filed:

Jun 13, 2005

Appl. No.:

11/152445

Inventors:

Kenneth Barnett - Oceanside CA, US
Brett C. Walker - San Diego CA, US
Kevin Gard - Raleigh NC, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H03G 3/30

US Classification:

330289, 330283

Abstract:

A radio frequency (RF) driver amplifier system and method that provides linear in decibel gain control is provided. The RF driver amplifier system comprises a linear transconductor receiving an input voltage and providing a controlled current based on input voltage received, temperature compensation circuitry for varying current from the linear transconductor according to absolute temperature, an exponential current controller receiving current varied according to temperature and providing an exponential current in response, and an inductive degeneration compensator receiving exponential current and providing a control current to driver amplifier circuitry, thereby compensating for inductive degeneration due to at least one inductor in the driver amplifier circuitry. Control current passes from the inductive degeneration compensator to the driver amplifier circuitry. Output gain from the driver amplifier circuitry varies linearly in decibels with respect to the input voltage.