Bryan H Wang

US Patent:

8151235, Apr 3, 2012

Filed:

Feb 24, 2009

Appl. No.:

12/380094

Inventors:

Lap Wai Chow - South Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US
Ronald P. Cocchi - Seal Beach CA, US

Assignee:

SypherMedia International, Inc. - Aliso Viejo CA

International Classification:

G06F 17/50

US Classification:

716121, 716116, 716117, 716128

Abstract:

A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells.

US Patent:

20200295763, Sep 17, 2020

Filed:

Jan 28, 2020

Appl. No.:

16/775077

Inventors:

- Sunnyvale CA, US
Lap Wai Chow - S. Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H03K 19/17736
G06F 21/14
H01L 27/02
H03K 19/17768
G06F 30/39

Abstract:

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

US Patent:

20170359071, Dec 14, 2017

Filed:

Aug 11, 2017

Appl. No.:

15/675418

Inventors:

- Westminster CA, US
Lap Wai Chow - S. Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US

Assignee:

SypherMedia International, Inc. - Westminster CA

International Classification:

H03K 19/177
H01L 27/02
G06F 21/14
G06F 17/50
H01L 27/118

Abstract:

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

US Patent:

20160197616, Jul 7, 2016

Filed:

Dec 30, 2015

Appl. No.:

14/985270

Inventors:

- Westminster CA, US
Lap Wai Chow - S. Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US

International Classification:

H03K 19/177
G06F 17/50

Abstract:

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.