Bryan Jason Wang

US Patent:

8151235, Apr 3, 2012

Filed:

Feb 24, 2009

Appl. No.:

12/380094

Inventors:

Lap Wai Chow - South Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US
Ronald P. Cocchi - Seal Beach CA, US

Assignee:

SypherMedia International, Inc. - Aliso Viejo CA

International Classification:

G06F 17/50

US Classification:

716121, 716116, 716117, 716128

Abstract:

A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells.

US Patent:

8418091, Apr 9, 2013

Filed:

Oct 13, 2009

Appl. No.:

12/578441

Inventors:

Lap Wai Chow - S. Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US
Ronald P. Cocchi - Seal Beach CA, US

Assignee:

SypherMedia International, Inc. - Aliso Viejo CA

International Classification:

G06F 17/50

US Classification:

716101, 716104, 716126

Abstract:

A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.

US Patent:

8510700, Aug 13, 2013

Filed:

Feb 9, 2012

Appl. No.:

13/370118

Inventors:

Ronald P. Cocchi - Seal Beach CA, US
Lap Wai Chow - South Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US

Assignee:

SypherMedia International, Inc. - Westminster CA

International Classification:

G06F 17/50

US Classification:

716121, 716116, 716117, 716128, 716139

Abstract:

A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

US Patent:

20130191803, Jul 25, 2013

Filed:

Mar 7, 2013

Appl. No.:

13/789267

Inventors:

James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US
Ronald P. Cocchi - Seal Beach CA, US

Assignee:

SypherMedia International, Inc. - Viejo CA

International Classification:

G06F 17/50

US Classification:

716121

Abstract:

A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logic cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.

US Patent:

20210249363, Aug 12, 2021

Filed:

Jan 25, 2021

Appl. No.:

17/157567

Inventors:

- San Jose CA, US
Bryan J. Wang - South Lake Tahoe CA, US
James P. Baukus - Westlake Village CA, US
Ronald P. Cocchi - Huntington Beach CA, US

Assignee:

Rambus Inc. - San Jose CA

International Classification:

H01L 23/00
H01L 29/66
H01L 29/423
H01L 29/417

Abstract:

A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

US Patent:

20210249364, Aug 12, 2021

Filed:

Jan 25, 2021

Appl. No.:

17/157579

Inventors:

- San Jose CA, US
Bryan J. Wang - South Lake Tahoe CA, US
James P. Baukus - Westlake Village CA, US
Ronald P. Cocchi - Huntington Beach CA, US

Assignee:

Rambus Inc. - San Jose CA

International Classification:

H01L 23/00
H01L 29/10
H01L 27/092
H01L 21/8238
H01L 29/66
H01L 29/78

Abstract:

A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

US Patent:

20210004515, Jan 7, 2021

Filed:

Jun 18, 2020

Appl. No.:

16/905724

Inventors:

- San Jose CA, US
Bryan J. Wang - South Lake Tahoe CA, US
James P. Baukus - Westlake Village CA, US
Ronald P. Cocchi - Huntington Beach CA, US

Assignee:

Rambus Inc. - San Jose CA

International Classification:

G06F 30/392
H01L 27/02
G06F 21/14
H03K 19/17736
H01L 27/118
G06F 30/39
G06F 30/394

Abstract:

The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.

US Patent:

20200295763, Sep 17, 2020

Filed:

Jan 28, 2020

Appl. No.:

16/775077

Inventors:

- Sunnyvale CA, US
Lap Wai Chow - S. Pasadena CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - South Lake Tahoe CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H03K 19/17736
G06F 21/14
H01L 27/02
H03K 19/17768
G06F 30/39

Abstract:

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.