Chang Zhong Lin

US Patent:

20230105736, Apr 6, 2023

Filed:

Sep 15, 2022

Appl. No.:

17/945493

Inventors:

- Short Hills NJ, US
Shankarram Subramanian - Chennai, IN
Karolina Anna Kierzkowski - Westfield NJ, US
Jahnab Kumar Deka - Guwahati, IN
Chang Lin - Riverside CT, US

Assignee:

THE DUN AND BRADSTREET CORPORATION - Short Hills NJ

International Classification:

G06F 18/2415
G06F 18/214
G06F 18/21
G06F 18/23211

Abstract:

A method that includes (a) receiving a training dataset, a testing dataset, a number of iterations, and a parameter space of possible parameter values that define a base model, (b) for the number of iterations, performing a parametric search process that produces a report that includes information concerning a plurality of machine learning models, where the parametric search process includes (i) generating a Bayesian optimized parameter space with an option to validate through Stratified Kfold cross validation, where an optimized parameter set includes training data from the training dataset, and testing data from the testing dataset, (ii) running the base model with the final optimized parameter set, thus yielding model results for the plurality of machine learning models, (iii) calculating Kolmogorov-Smirnov (KS) statistics for the model results, and (iv) saving the model results and the KS statistics to the report, and (c) sending the report to a user device.

US Patent:

20170207152, Jul 20, 2017

Filed:

Apr 3, 2017

Appl. No.:

15/478064

Inventors:

- Santa Clara CA, US
Lilia May - Chandler AZ, US
Rajen S. Sidhu - Chandler AZ, US
Mukul P. Renavikar - Chandler AZ, US
Ashay A. Dani - Chandler AZ, US
Edward R. Prack - Phoenix AZ, US
Carl L. Deppisch - Chandler AZ, US
Anna M. Prakash - Chandler AZ, US
James C. Matayabas - Gilber AZ, US
Jason Jieping Zhang - Chandler AZ, US
Srinivasa R. Aravamudhan - Beaverton OR, US
Chang Lin - Portland OR, US

International Classification:

H01L 23/498
H01L 23/31
H01L 25/00
H01L 21/48
H01L 21/56
H01L 21/768
H01L 25/065
H01L 23/00

Abstract:

An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

US Patent:

20150255415, Sep 10, 2015

Filed:

Mar 5, 2014

Appl. No.:

14/198479

Inventors:

Thomas J. De Bonis - Tempe AZ, US
Lilia May - Chandler AZ, US
Rajen S. Sidhu - Chandler AZ, US
Mukul P. Renavikar - Chandler AZ, US
Ashay A. Dani - Chandler AZ, US
Edward R. Prack - Phoenix AZ, US
Carl L. Deppisch - Chandler AZ, US
Anna M. Prakash - Chandler AZ, US
Jason Jieping Zhang - Chandler AZ, US
Srinivasa R. Aravamudhan - Beaverton OR, US
Chang Lin - Portland OR, US

International Classification:

H01L 23/00
H01L 25/065
H01L 23/498
H01L 23/31
H01L 21/56
H01L 21/768

Abstract:

An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.