Chang S Yang

US Patent:

20120216089, Aug 23, 2012

Filed:

Feb 23, 2011

Appl. No.:

13/032732

Inventors:

Wei Chen - San Diego CA, US
Yucong Tao - San Diego CA, US
Matthew L. Severson - San Diego CA, US
Jeffrey R. Gemar - San Diego CA, US
Chang Yong Yang - Fayetteville NC, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 11/00
H03L 5/00
G01R 31/40
G06F 19/00

US Classification:

714727, 700121, 327333, 32476401, 714E1102

Abstract:

In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit.

US Patent:

20140223250, Aug 7, 2014

Filed:

Feb 4, 2014

Appl. No.:

14/172292

Inventors:

- San Diego CA, US
Yucong Tao - San Diego CA, US
Matthew L. Severson - San Diego CA, US
Jeffrey R. Gemar - San Diego CA, US
Chang Yong Yang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G01R 31/3177

US Classification:

714727

Abstract:

Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.