Chao Liu

US Patent:

7772821, Aug 10, 2010

Filed:

Jun 12, 2007

Appl. No.:

11/818093

Inventors:

Chao Liu - San Jose CA, US
Anthonius Bakker - Morgan Hill CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F 1/00

US Classification:

323283

Abstract:

A digital current share bus interface connects to a power module which provides a signal representative of its output current, and adjusts the module's output current in response to a control signal received from the interface. A data formatting module receives the output current signal and generates a digital word that varies with the current; the bits of the word are coupled to a current share bus. A comparator module receives digital words conveyed via the bus and generated by the data formatting module at respective inputs, and provides the control signal to the power module so as to adjust its output current to match the current value represented by the digital word on the bus. In a typical implementation, multiple power modules are coupled to the current share bus via respective interfaces, with the output currents of all the power modules connected in parallel.

US Patent:

7776758, Aug 17, 2010

Filed:

Jul 28, 2006

Appl. No.:

11/495188

Inventors:

Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 21/31

US Classification:

438758, 438128, 438507, 438509, 977891, 257E21209

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices).

US Patent:

7968273, Jun 28, 2011

Filed:

Jul 27, 2007

Appl. No.:

11/881739

Inventors:

Jian Chen - Mountain View CA, US
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
Madhuri L. Nallabolu - Sunnyvale CA, US
J. Wallace Parce - Palo Alto CA, US
Srikanth Ranganathan - Mountain View CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

G03F 7/26

US Classification:

430311, 430328, 430394, 430330

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

US Patent:

7976646, Jul 12, 2011

Filed:

Aug 18, 2006

Appl. No.:

11/506769

Inventors:

Srikanth Ranganathan - Mountain View CA, US
Paul Bernatis - Sunnyvale CA, US
Joel Gamoras - Vallejo CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

C22C 5/04
B32B 15/02

US Classification:

148430, 420462, 428546

Abstract:

Methods for producing electronic grade metal nanostructures having low levels of contaminants are provided. Monolayer arrays, populations, and devices including such electronic grade nanostructures are described. In addition, novel methods and compositions for production of Group 10 metal nanostructures and for production of ruthenium nanostructures are provided, along with methods for recovering nanostructures from suspension.

US Patent:

8507390, Aug 13, 2013

Filed:

Jun 29, 2010

Appl. No.:

12/803568

Inventors:

Jian Chen - Sunnyvale CA, US
Karen Chu Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US

Assignee:

Sandisk Corporation - Milpitas CA

International Classification:

H01L 21/3105

US Classification:

438782, 438128, 438674, 977845, 977855, 257E21241

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices).

US Patent:

8558304, Oct 15, 2013

Filed:

Apr 29, 2011

Appl. No.:

13/098082

Inventors:

Jian Chen - Sunnyvale CA, US
Xiangfeng Duan - Los Angeles CA, US
Chao Liu - San Jose CA, US
Madhuri Nallabolu - Sunnyvale CA, US
J. Wallace Parce - Palo Alto CA, US
Srikanth Ranganathan - Mountain View CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

H01L 29/792

US Classification:

257325, 257314, 257315, 257406, 257E29039, 438311, 438507, 438509, 438128, 977891

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

US Patent:

20060040103, Feb 23, 2006

Filed:

Jun 7, 2005

Appl. No.:

11/147670

Inventors:

Jeffery Whiteford - Belmont CA, US
Rhett Brewer - Sunnyvale CA, US
Mihai Buretea - San Francisco CA, US
Jian Chen - Mountain View CA, US
Karen Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
William Freeman - San Mateo CA, US
David Heald - Solvang CA, US
Francisco Leon - Palo Alto CA, US
Chao Liu - San Jose CA, US
Andreas Meisel - San Francisco CA, US
Kyu Min - San Jose CA, US
J. Parce - Palo Alto CA, US
Erik Scher - San Francisco CA, US

Assignee:

NANOSYS, Inc. - Palo Alto CA

International Classification:

B32B 5/16

US Classification:

428403000

Abstract:

Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.

US Patent:

20080032134, Feb 7, 2008

Filed:

Feb 13, 2007

Appl. No.:

11/706730

Inventors:

Jeffery Whiteford - Belmont CA, US
Rhett Brewer - Sunnyvale CA, US
Mihai Buretea - San Francisco CA, US
Jian Chen - Mountain View CA, US
Karen Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
William Freeman - San Mateo CA, US
David Heald - Solvang CA, US
Francisco Leon - Palo Alto CA, US
Chao Liu - San Jose CA, US
Andreas Meisel - San Francisco CA, US
Kyu Min - San Jose CA, US
J. Parce - Palo Alto CA, US
Erik Scher - San Francisco CA, US

Assignee:

NANOSYS, Inc. - Palo Alto CA

International Classification:

B32B 5/16
B32B 15/04
B32B 17/06

US Classification:

428402240

Abstract:

Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.