Chao Yue Liu

US Patent:

7501315, Mar 10, 2009

Filed:

Jun 7, 2005

Appl. No.:

11/148001

Inventors:

David L. Heald - Solvang CA, US
Karen Chu Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 21/82
H01L 27/10

US Classification:

438128, 438674, 438758, 257E21209, 977845, 977855

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices).

US Patent:

7772821, Aug 10, 2010

Filed:

Jun 12, 2007

Appl. No.:

11/818093

Inventors:

Chao Liu - San Jose CA, US
Anthonius Bakker - Morgan Hill CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F 1/00

US Classification:

323283

Abstract:

A digital current share bus interface connects to a power module which provides a signal representative of its output current, and adjusts the module's output current in response to a control signal received from the interface. A data formatting module receives the output current signal and generates a digital word that varies with the current; the bits of the word are coupled to a current share bus. A comparator module receives digital words conveyed via the bus and generated by the data formatting module at respective inputs, and provides the control signal to the power module so as to adjust its output current to match the current value represented by the digital word on the bus. In a typical implementation, multiple power modules are coupled to the current share bus via respective interfaces, with the output currents of all the power modules connected in parallel.

US Patent:

7776758, Aug 17, 2010

Filed:

Jul 28, 2006

Appl. No.:

11/495188

Inventors:

Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 21/31

US Classification:

438758, 438128, 438507, 438509, 977891, 257E21209

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices).

US Patent:

7807217, Oct 5, 2010

Filed:

Jul 5, 2006

Appl. No.:

11/481388

Inventors:

Nisha Shukla - Pittsburgh PA, US
Timothy John Klemmer - Pittsburgh PA, US
Dieter Klaus Weller - San Jose CA, US
Chao Liu - San Jose CA, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

B05D 1/12

US Classification:

427127

Abstract:

A method comprises: heating a solution of platinum acetylacetonate, Fe(CO), oleic acid, and oleylamine in dichlorobenzene to a reflux temperature, refluxing the solution, and using the solution to deposit FePt nanoparticles. A magnetic storage medium that includes cubic FePt particles is also provided.

US Patent:

7968273, Jun 28, 2011

Filed:

Jul 27, 2007

Appl. No.:

11/881739

Inventors:

Jian Chen - Mountain View CA, US
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
Madhuri L. Nallabolu - Sunnyvale CA, US
J. Wallace Parce - Palo Alto CA, US
Srikanth Ranganathan - Mountain View CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

G03F 7/26

US Classification:

430311, 430328, 430394, 430330

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

US Patent:

7976646, Jul 12, 2011

Filed:

Aug 18, 2006

Appl. No.:

11/506769

Inventors:

Srikanth Ranganathan - Mountain View CA, US
Paul Bernatis - Sunnyvale CA, US
Joel Gamoras - Vallejo CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

C22C 5/04
B32B 15/02

US Classification:

148430, 420462, 428546

Abstract:

Methods for producing electronic grade metal nanostructures having low levels of contaminants are provided. Monolayer arrays, populations, and devices including such electronic grade nanostructures are described. In addition, novel methods and compositions for production of Group 10 metal nanostructures and for production of ruthenium nanostructures are provided, along with methods for recovering nanostructures from suspension.

US Patent:

8143703, Mar 27, 2012

Filed:

Nov 5, 2008

Appl. No.:

12/291101

Inventors:

David L. Heald - Solvang CA, US
Karen Chu Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 29/06

US Classification:

257618, 977755, 977936, 977938

Abstract:

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices).

US Patent:

8383254, Feb 26, 2013

Filed:

Sep 28, 2010

Appl. No.:

12/891838

Inventors:

Nisha Shukla - Pittsburgh PA, US
Timothy John Klemmer - Pittsburgh PA, US
Dieter Klaus Weller - San Jose CA, US
Chao Liu - San Jose CA, US

Assignee:

Seagate Technology LLC - Cupertino CA

International Classification:

G11B 5/65

US Classification:

428827, 428829, 4288361

Abstract:

An apparatus includes a substrate, a magnetically soft underlayer on the substrate, and a plurality of generally cubic FePt nanoparticles on the magnetically soft underlayer, wherein the nanoparticles have a magnetization in a direction substantially normal to a surface of the magnetically soft underlayer. The FePt nanoparticles can have magnetically easy axes perpendicular to the surface of the soft underlayer.