Chao B Song

US Patent:

20220182065, Jun 9, 2022

Filed:

Sep 28, 2021

Appl. No.:

17/449250

Inventors:

- San Diego CA, US
Chao SONG - San Diego CA, US
Karthik NAGARAJAN - Poway CA, US

International Classification:

H03M 1/06
H03M 1/82

Abstract:

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

US Patent:

20200118921, Apr 16, 2020

Filed:

Oct 12, 2018

Appl. No.:

16/158742

Inventors:

- San Diego CA, US
Ye LU - San Diego CA, US
Chao SONG - San Diego CA, US

International Classification:

H01L 23/522
H01L 23/58
H01L 49/02
H01G 4/06

Abstract:

Certain aspects of the present disclosure provide a metal-on-metal (MoM) capacitor with metal layers, each layer having two different electrical conductors with orthogonally-arranged conductive arteries and orthogonally-oriented conductive fingers. One exemplary MoM capacitor generally includes a plurality of metal layers, wherein a first metal layer in the plurality of metal layers comprises a first electrical conductor providing a first node of the MoM capacitor and a second electrical conductor providing a second node of the MoM capacitor. According to aspects, the first electrical conductor comprises a first plurality of conductive fingers and the second electrical conductor comprises a second plurality of conductive fingers. Further, conductive fingers of the first plurality of conductive fingers are interdigitated with conductive fingers of the second plurality of conductive fingers. Additionally, the first electrical conductor in the first metal layer is oriented orthogonal to the second electrical conductor in the first metal layer.

US Patent:

20200111865, Apr 9, 2020

Filed:

Oct 9, 2018

Appl. No.:

16/155694

Inventors:

- San Diego CA, US
Junjing BAO - San Diego CA, US
Haitao CHENG - San Jose CA, US
Chao SONG - San Diego CA, US

International Classification:

H01L 49/02
H01L 23/522

Abstract:

A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.

US Patent:

20200075582, Mar 5, 2020

Filed:

Aug 28, 2018

Appl. No.:

16/115206

Inventors:

- San Diego CA, US
Chao SONG - San Diego CA, US
Haitao CHENG - San Diego CA, US

International Classification:

H01L 27/06
H01L 27/02
H01L 23/522
H01L 49/02

Abstract:

A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.

US Patent:

20200066829, Feb 27, 2020

Filed:

Aug 21, 2018

Appl. No.:

16/106160

Inventors:

- San Diego CA, US
Chao Song - San Diego CA, US
Ye Lu - San Diego CA, US

International Classification:

H01L 49/02
H01F 17/00
H01L 23/522
H01L 27/08

Abstract:

Aspects generally relate to adjusting, or lowering, the Q of an inductor. In one embodiment, an integrated circuit includes an inductor and a conductive closed ring inside a periphery of the inductor. In another embodiment, there can be a plurality of closed rings inside the periphery of the inductor. The conductive closed rings are magnetically coupled to the inductor to adjust the Q.

US Patent:

20200051718, Feb 13, 2020

Filed:

Aug 8, 2018

Appl. No.:

16/058928

Inventors:

- San Diego CA, US
Chao SONG - San Diego CA, US
Ye LU - San Diego CA, US

International Classification:

H01C 3/02
H01L 49/02
H01L 27/02
G06F 17/50
H01C 3/16
H01C 17/04

Abstract:

A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.

US Patent:

20200043863, Feb 6, 2020

Filed:

Aug 1, 2018

Appl. No.:

16/051525

Inventors:

- San Diego CA, US
Ye LU - San Diego CA, US
Chao SONG - San Diego CA, US

International Classification:

H01L 23/552
H01L 23/66

Abstract:

Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.

US Patent:

20200044013, Feb 6, 2020

Filed:

Aug 2, 2018

Appl. No.:

16/053124

Inventors:

- San Diego CA, US
Haitao CHENG - San Diego CA, US
Chao SONG - San Diego CA, US

International Classification:

H01L 49/02
H01L 21/02
H01L 21/283
H01L 21/311

Abstract:

A capacitor includes a first conductive element having a plurality of first conductive fingers and a second conductive element having a plurality of second conductive fingers. The first conductive fingers are interdigitated with the second conductive fingers. The capacitor further includes a conformally deposited dielectric material that separates the plurality of first conductive fingers from the plurality of second conductive fingers.