Charles C Chiang

US Patent:

7289933, Oct 30, 2007

Filed:

Nov 4, 2005

Appl. No.:

11/267776

Inventors:

Jianfeng Luo - Fremont CA, US
Qing Su - Sunnyvale CA, US
Charles Chiang - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G01B 11/24
H01L 21/31

US Classification:

702167, 438780

Abstract:

A dimension of a conductive material in a semiconductor wafer is determined by a computer that treats as identical (a) volume of the conductive material which is proportional to an effective surface area of sidewalls of an insulative trench and (b) volume of the conductive material derived from geometry based on a predetermined amount by which width of a conductive trench (if present) in the conductive material differs from width of the insulative trench. In some embodiments, the computer computes the effective surface area as the product of trench depth and a layout parameter, either or both of which may be partially or wholly empirically determined from a test wafer containing several topographies. The computer computes the dimension assuming one topography and validates the assumption if a predetermined condition is met. If the condition is not met, the computer re-computes the dimension, assuming another topography.

US Patent:

7346865, Mar 18, 2008

Filed:

Nov 1, 2004

Appl. No.:

10/978946

Inventors:

Qing Su - Sunnyvale CA, US
Subarnarekha Sinha - Foster City CA, US
Charles C. Chiang - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5

Abstract:

Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

US Patent:

7496883, Feb 24, 2009

Filed:

May 11, 2005

Appl. No.:

11/127694

Inventors:

Subarnarekha Sinha - Foster City CA, US
Charles C. Chiang - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 21, 716 19, 716 20, 430 5, 430 30

Abstract:

One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout such that the PSM-layout is phase-assignable if and only if the phase-conflict graph is bipartite. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. The system can also be used to correct a given set of phase conflicts in a PSM-layout.

US Patent:

7503029, Mar 10, 2009

Filed:

Mar 31, 2006

Appl. No.:

11/395006

Inventors:

Subarnarekha Sinha - Menlo Park CA, US
Hailong Yao - Beijing, CN
Charles C. Chiang - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 4, 716 5

Abstract:

A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments.

US Patent:

7509622, Mar 24, 2009

Filed:

Apr 17, 2006

Appl. No.:

11/379043

Inventors:

Subarnarekha Sinha - Menlo Park CA, US
Jianfeng Luo - Fremont CA, US
Charles C. Chiang - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50
G06F 19/00

US Classification:

716 21, 716 8, 700119, 700120, 700121

Abstract:

The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the “case” of each tile identified. Exemplary cases can include conformal fill, over fill, super fill, or super/over fill (if the ECP model cannot distinguish between super and over fill cases). One or more undesired tile cases can be converted to a desired tile case. Then, a height difference between tiles can be minimized. Dummy features can be inserted in the layout to perform the conversion and to minimize the height difference between tiles. Minimizing the CMP-effective density difference between tiles with ECP considerations can be performed to further improve planarization.

US Patent:

7543255, Jun 2, 2009

Filed:

Mar 16, 2007

Appl. No.:

11/725007

Inventors:

Subarnarekha Sinha - Menlo Park CA, US
Qing Su - Sunnyvale CA, US
Charles C. Chiang - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 2

Abstract:

One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine local critical-area-ratios and optimization potentials for a set of wire-segments. The system can then select a wire segment, and compare its local critical-area-ratio with a global critical-area-ratio. Next, the system can use the result of the comparison to determine a layout optimization. The system can then apply the layout optimization to the wire segment to obtain an improved layout.

US Patent:

7703067, Apr 20, 2010

Filed:

Mar 31, 2006

Appl. No.:

11/394466

Inventors:

Subarnarekha Sinha - Menlo Park CA, US
Charles C. Chiang - San Jose CA, US

Assignee:

SYNOPSYS, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 4, 716 5, 716 11

Abstract:

A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i. e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout.

US Patent:

7707526, Apr 27, 2010

Filed:

May 25, 2007

Appl. No.:

11/805916

Inventors:

Qing Su - Sunnyvale CA, US
Charles C. Chiang - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 19, 716 20, 716 21

Abstract:

One embodiment of the present invention provides a system that predicts a manufacturing yield of a chip. During operation, the system first receives a chip layout. Next, the system identifies hotspots within the chip layout, wherein a hotspot is a location within the chip layout wherein a yield-indicative variable value falls in a low manufacturable range. The system then obtains yield scores for the hotspots, wherein a yield score indicates a failure probability for a corresponding hotspot. Next, the system predicts the manufacturing yield for the chip based on the hotspots and the yield scores for the hotspots.