Cheng Wang

US Patent:

6454508, Sep 24, 2002

Filed:

May 1, 1998

Appl. No.:

09/070854

Inventors:

Masato M. Toshima - Sunnyvale CA
Phil M. Salzman - San Jose CA
Steven C. Murdoch - Palo Alto CA
Cheng Wang - San Jose CA
Mark A. Stenholm - San Jose CA
James Howard - San Jose CA
Leonard Hall - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B65G 4905

US Classification:

414217, 414940, 414939, 118719

Abstract:

A workpiece loading interface is included within a workpiece processing system which processes workpieces, typically wafers, in a vacuum. The workpiece loading interface includes two separate chambers. Each chamber may be separately pumped down. Thus, while a first cassette of wafers, from a first chamber is being accessed, a second cassette of wafers may be loaded in the second chamber and the second chamber pumped down. Each chamber is designed to minimize intrusion to a clean room. Thus a door to each chamber has a mechanism which, when opening the door, first moves the door slightly away from an opening in the chamber and then the door is moved down parallel to the chamber. After the door is opened, a cassette of wafers is lowered through the opening in a motion much like a drawbridge. The cassette may be pivoted within the chamber when the position from which wafers are accessed from the cassette differs from the position from which the cassette is lowered out of the chamber.

US Patent:

6599076, Jul 29, 2003

Filed:

Aug 19, 2002

Appl. No.:

10/223539

Inventors:

Masato M. Toshima - Sunnyvale CA
Phil M. Salzman - San Jose CA
Steven C. Murdoch - Palo Alto CA
Cheng Wang - San Jose CA
Mark A. Stenholm - San Jose CA
James Howard - San Jose CA
Leonard Hall - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B65G 4907

US Classification:

414217, 414939

Abstract:

A workpiece loading interface is included within a workpiece processing system which processes workpieces, typically wafers, in a vacuum. The workpiece loading interface includes two separate chambers. Each chamber may be separately pumped down. Thus, while a first cassette of wafers, from a first chamber is being accessed, a second cassette of wafers may be loaded in the second chamber and the second chamber pumped down. Each chamber is designed to minimize intrusion to a clean room. Thus a door to each chamber has a mechanism which, when opening the door, first moves the door slightly away from an opening in the chamber and then the door is moved down parallel to the chamber. After the door is opened, a cassette of wafers is lowered through the opening in a motion much like a drawbridge. The cassette may be pivoted within the chamber when the position from which wafers are accessed from the cassette differs from the position from which the cassette is lowered out of the chamber.

US Patent:

7506217, Mar 17, 2009

Filed:

Dec 30, 2005

Appl. No.:

11/325773

Inventors:

Edson Borin - Campinas, BR
Cheng C. Wang - San Jose CA, US
Youfeng Wu - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 51, 714732

Abstract:

A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.

US Patent:

7694281, Apr 6, 2010

Filed:

Sep 30, 2005

Appl. No.:

11/241527

Inventors:

Cheng Wang - San Jose CA, US
Bixia Zheng - Palo Alto CA, US
Ho-seop Kim - Cupertino CA, US
Mauricio Breternitz, Jr. - Austin TX, US
Youfeng Wu - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/44

US Classification:

717128

Abstract:

A first potential hot trace of a program is determined. A second potential hot trace of the program is determined. A common path from the first potential hot trace and the second potential hot trace is selected as the selected hot trace of the program.

US Patent:

7757221, Jul 13, 2010

Filed:

Sep 30, 2005

Appl. No.:

11/241610

Inventors:

Bixia Zheng - Palo Alto CA, US
Cheng C. Wang - Cupertino CA, US
Ho-seop Kim - Cupertino CA, US
Mauricio Breternitz, Jr. - Austin TX, US
Youfeng Wu - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717136, 717137, 717140, 717145, 717156, 717151, 717152

Abstract:

A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

US Patent:

7802136, Sep 21, 2010

Filed:

Dec 28, 2006

Appl. No.:

11/648486

Inventors:

Cheng Wang - Santa Clara CA, US
Youfeng Wu - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 19

Abstract:

A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point to the recovery block. A control flow edge is inserted from the recovery block to a entry point of the transaction. Checkpoint code is inserted before the entry point to backup live-in registers in backup storage elements and recovery code is inserted in the recovery block to restore the live-in registers from the backup storage elements in response to an abort of the transaction.

US Patent:

7818744, Oct 19, 2010

Filed:

Dec 30, 2005

Appl. No.:

11/325925

Inventors:

Cheng C. Wang - Sunnyvale CA, US
Youfeng Wu - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/46
G06F 5/00

US Classification:

718100, 710 52, 710 56

Abstract:

An apparatus and method for redundant transient fault detection. In one embodiment, the method includes the replication of an application into two communicating threads, a leading thread and a trailing thread. The trailing thread may repeat computations performed by the leading thread to detect transient faults, referred to herein as “soft errors. ” A first in, first out (FIFO) buffer of shared memory is reserved for passing data between the leading thread and the trailing thread. The FIFO buffer may include a buffer head variable to write data to the FIFO buffer and a buffer tail variable to read data from the FIFO buffer. In one embodiment, data passing between the leading thread data buffering is restricted according to a data unit size and thread synchronization between a leading thread and the trailing thread is limited to buffer overflow/underflow detection. Other embodiments are described and claimed.

US Patent:

7844946, Nov 30, 2010

Filed:

Sep 26, 2006

Appl. No.:

11/535205

Inventors:

Youfeng Wu - Palo Alto CA, US
Cheng Wang - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/44
G06F 9/46

US Classification:

717119, 717120, 717136, 717149, 718104, 718105

Abstract:

Methods and an apparatus for forming a transaction object instruction construct are provided. An example method translates a source instruction construct to form a transactional objective instruction construct, executes the transactional objective instruction construct, intercepts an aborted transaction associated with the transactional objective instruction construct during execution, maintains a graph of nodes and edges associated with the executed transactional objective instruction construct to predict a deadlock situation, and resolves the deadlock situation associated with the transactional objective instruction construct based on the graph.