Cheng P Wang

US Patent:

7757221, Jul 13, 2010

Filed:

Sep 30, 2005

Appl. No.:

11/241610

Inventors:

Bixia Zheng - Palo Alto CA, US
Cheng C. Wang - Cupertino CA, US
Ho-seop Kim - Cupertino CA, US
Mauricio Breternitz, Jr. - Austin TX, US
Youfeng Wu - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717136, 717137, 717140, 717145, 717156, 717151, 717152

Abstract:

A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

US Patent:

7844946, Nov 30, 2010

Filed:

Sep 26, 2006

Appl. No.:

11/535205

Inventors:

Youfeng Wu - Palo Alto CA, US
Cheng Wang - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/44
G06F 9/46

US Classification:

717119, 717120, 717136, 717149, 718104, 718105

Abstract:

Methods and an apparatus for forming a transaction object instruction construct are provided. An example method translates a source instruction construct to form a transactional objective instruction construct, executes the transactional objective instruction construct, intercepts an aborted transaction associated with the transactional objective instruction construct during execution, maintains a graph of nodes and edges associated with the executed transactional objective instruction construct to predict a deadlock situation, and resolves the deadlock situation associated with the transactional objective instruction construct based on the graph.

US Patent:

7865885, Jan 4, 2011

Filed:

Sep 27, 2006

Appl. No.:

11/528801

Inventors:

Youfeng Wu - Palo Alto CA, US
Cheng Wang - Santa Clara CA, US
Ho-seop Kim - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717151, 717146, 717153, 717154, 717159, 717160, 717161, 717136, 717137, 717140, 717141

Abstract:

Dynamic optimization of application code is performed by selecting a portion of the application code as a possible transaction. A transaction has a property that when it is executed, it is either atomically committed or atomically aborted. Determining whether to convert the selected portion of the application code to a transaction includes determining whether to apply at least one of a group of code optimizations to the portion of the application code. If it is determined to apply at least one of the code optimizations of the group of optimizations to the portion of application code, then the optimization is applied to the portion of the code and the portion of the code is converted to a transaction.

US Patent:

8156480, Apr 10, 2012

Filed:

Sep 29, 2006

Appl. No.:

11/537287

Inventors:

Youfeng Wu - Palo Alto CA, US
Cheng Wang - Santa Clara CA, US
Ho-Seop Kim - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717140

Abstract:

Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.

US Patent:

8418156, Apr 9, 2013

Filed:

Dec 16, 2009

Appl. No.:

12/639251

Inventors:

Cheng Wang - San Ramon CA, US
Youfeng Wu - Palo Alto CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717151, 717153, 717154, 717159, 717160, 717161, 712245, 712246, 712247, 712248, 718104

Abstract:

Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and combined for the TSC region. Binary optimization operations may be performed on the TSC region to enable the code to run more efficiently by, for example, reordering load and store instructions. In the first stage, load operations in the region may be committed atomically and in the second stage, store operations in the region may be committed atomically.

US Patent:

20110320766, Dec 29, 2011

Filed:

Jun 29, 2010

Appl. No.:

12/826107

Inventors:

Youfeng Wu - Palo Alto CA, US
Shiliang Hu - Los Altos CA, US
Edson Borin - San Jose CA, US
Cheng C. Wang - San Ramon CA, US
Mauricio Breternitz, JR. - Austin TX, US
Wei Liu - San Jose CA, US

International Classification:

G06F 9/30
G06F 15/76

US Classification:

712 28, 712 1, 712E09016

Abstract:

An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

US Patent:

20120016853, Jan 19, 2012

Filed:

Sep 27, 2011

Appl. No.:

13/246678

Inventors:

Cheng Wang - San Ramon CA, US
Youfeng Wu - Palo Alto CA, US
Wei-Yu Chen - Santa Clara CA, US
Bratin Saha - Santa Clara CA, US
Ali Reza Adl-Tabatabai - San Jose CA, US

International Classification:

G06F 7/00

US Classification:

707703, 707E17005

Abstract:

A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.

US Patent:

20120079245, Mar 29, 2012

Filed:

Sep 25, 2010

Appl. No.:

12/890638

Inventors:

Cheng Wang - San Ramon CA, US
Edson Borin - San Jose CA, US
Youfeng Wu - Palo Alto CA, US
Shiliang Hu - Los Altos CA, US
Wei Liu - San Jose CA, US
Mauricio Breternitz, JR. - Austin TX, US

International Classification:

G06F 9/312
G06F 9/38
G06F 9/30

US Classification:

712208, 712228, 712E09028, 712E09033, 712E09045

Abstract:

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.