Cheng Hsiung Wang

US Patent:

8443353, May 14, 2013

Filed:

Sep 25, 2010

Appl. No.:

12/890639

Inventors:

Mauricio Breternitz, Jr. - Austin TX, US
Youfeng Wu - Palo Alto CA, US
Cheng Wang - San Ramon CA, US
Edson Borin - San Jose CA, US
Shiliang Hu - Los Altos CA, US
Craig B. Zilles - Champaign IL, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717153

Abstract:

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

US Patent:

8549504, Oct 1, 2013

Filed:

Sep 25, 2010

Appl. No.:

12/890639

Inventors:

Mauricio Breternitz, Jr. - Austin TX, US
Youfeng Wu - Palo Alto CA, US
Cheng Wang - San Ramon CA, US
Edson Borin - San Jose CA, US
Shiliang Hu - Los Altos CA, US
Craig B. Zilles - Champaign IL, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/45

US Classification:

717153

Abstract:

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

US Patent:

20130318507, Nov 28, 2013

Filed:

May 13, 2013

Appl. No.:

13/893238

Inventors:

Mauricio Breternitz, JR. - Austin TX, US
Youfeng Wu - Palo Alto CA, US
Cheng Wang - San Ramon CA, US
Edson Borin - San Jose CA, US
Shiliang Hu - Los Altos CA, US
Craig B. Zilles - Champaign IL, US

International Classification:

G06F 11/36

US Classification:

717129

Abstract:

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.