Chi Wan Cheng

US Patent:

7389487, Jun 17, 2008

Filed:

Apr 28, 1998

Appl. No.:

09/069054

Inventors:

King W. Chan - Los Altos CA, US
William C. T. Shu - Palo Alto CA, US
Sinan Kaptanoglu - Belmont CA, US
Chi Fung Cheng - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 17, 716 16

Abstract:

An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

US Patent:

7589649, Sep 15, 2009

Filed:

May 4, 2007

Appl. No.:

11/800554

Inventors:

Arshan Aga - Mountain View CA, US
Chi Fung Cheng - San Jose CA, US
Hongxin Song - Sunnyvale CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 1/06

US Classification:

341118, 341119, 341120, 341139, 341143, 341155

Abstract:

Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator. The method generally includes the steps of coupling an analog storage device and the read channel with an AC-coupling circuit, detecting a baseline or a component of an analog signal at a node downstream from the AC-coupling circuit, and configuring a current device to modify the analog signal in response to detecting the baseline or a component of the analog signal, wherein the current device is coupled to a node downstream from the AC-coupling circuit and upstream from a signal processor configured to operate on the analog signal.

US Patent:

7825737, Nov 2, 2010

Filed:

Dec 15, 2008

Appl. No.:

12/334701

Inventors:

Steve Fang - Sunnyvale CA, US
Chi Fung Cheng - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03L 7/087

US Classification:

331 11, 331 1 A, 331 8, 331 17, 331 25

Abstract:

A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

US Patent:

20080204074, Aug 28, 2008

Filed:

May 2, 2008

Appl. No.:

12/114143

Inventors:

King W. Chan - Los Altos CA, US
William C.T. Shu - Palo Alto CA, US
Sinan Kaptanoglu - Belmont CA, US
Chi Fung Cheng - San Jose CA, US

Assignee:

ACTEL CORPORATION - Mountain View CA

International Classification:

H03K 19/177

US Classification:

326 41

Abstract:

An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.