Chi Hin Chui

US Patent:

7271458, Sep 18, 2007

Filed:

Mar 31, 2003

Appl. No.:

10/404876

Inventors:

Chi On Chui - San Mateo CA, US
Krishna C. Saraswat - Saratoga CA, US
Baylor B. Triplett - La Honda CA, US
Paul McIntyre - Sunnyvale CA, US

Assignee:

The Board of Trustees of the LeLand Stanford Junior University - Palo Alto CA

International Classification:

H01L 29/76

US Classification:

257410, 257411

Abstract:

Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiOequivalent (“T”). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a high-k dielectric material. A dielectric layer is then formed over the electrode surface material with the high-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.

US Patent:

7435987, Oct 14, 2008

Filed:

Mar 27, 2007

Appl. No.:

11/728890

Inventors:

Chi On Chui - Los Angeles CA, US
Prashant Majhi - Austin TX, US
Wilman Tsai - Saratoga CA, US
Jack T. Kavalieros - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31/0328

US Classification:

257 14, 257 19, 257194, 257E29069, 257E29072

Abstract:

In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (SiGe), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (SiGe(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of SiGe(C). Other embodiments are described and claimed.

US Patent:

7495313, Feb 24, 2009

Filed:

Jul 22, 2005

Appl. No.:

11/188140

Inventors:

Ammar Munir Nayfeh - Stanford CA, US
Chi On Chui - San Mateo CA, US
Krishna C. Saraswat - Saratoga CA, US
Takao Yonehara - Kanagawa-Ken, JP

Assignee:

Board of Trustees of the Leland Stanford Junior University - Palo Alto CA
Canon Kabushiki Kaisha - Tokyo

International Classification:

H01L 27/082

US Classification:

257593, 257 63, 257 64, 257 65, 257E21201, 438341, 438413, 438416, 438350

Abstract:

Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.

US Patent:

7629603, Dec 8, 2009

Filed:

Jun 9, 2006

Appl. No.:

11/450744

Inventors:

Chi On Chui - San Mateo CA, US
Prashant Majhi - Austin TX, US
Wilman Tsai - Saratoga CA, US
Jack T. Kavalieros - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31/00

US Classification:

257 18, 257254, 257417, 257E29193, 257213

Abstract:

A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate. Thus, a strained crystalline substrate may be provided. In another embodiment, a semiconductor region with a crystalline lattice of three or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate.

US Patent:

7772078, Aug 10, 2010

Filed:

Aug 26, 2008

Appl. No.:

12/198838

Inventors:

Ammar Munir Nayfeh - Stanford CA, US
Chi On Chui - San Mateo CA, US
Krishna C. Saraswat - Saratoga CA, US
Takao Yonehara - Kawasaki, JP

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA
Canon Kabushiki Kaisha - Tokyo

International Classification:

H01L 21/76

US Classification:

438341, 438413, 438416, 438481, 438E21201

Abstract:

Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.

US Patent:

7919381, Apr 5, 2011

Filed:

Mar 8, 2010

Appl. No.:

12/719796

Inventors:

Ammar Munir Nayfeh - Stanford CA, US
Chi On Chui - San Mateo CA, US
Krishna C. Saraswat - Saratoga CA, US
Takao Yonehara - Kawasaki, JP

Assignee:

Canon Kabushiki Kaisha - Tokyo
The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

H01L 21/76

US Classification:

438341, 438413, 438416, 438481, 438E21201

Abstract:

Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.

US Patent:

7928426, Apr 19, 2011

Filed:

Mar 27, 2007

Appl. No.:

11/728891

Inventors:

Chi On Chui - Los Angeles CA, US
Prashant Majhi - Austin TX, US
Wilman Tsai - Saratoga CA, US
Jack T. Kavalieros - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/06

US Classification:

257 24, 257E21702, 257E29168

Abstract:

In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

US Patent:

8237153, Aug 7, 2012

Filed:

Mar 11, 2011

Appl. No.:

13/046061

Inventors:

Chi On Chui - Los Angeles CA, US
Prashant Majhi - Austin TX, US
Wilman Tsai - Saratoga CA, US
Jack T. Kavalieros - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/778

US Classification:

257 24, 257E21702, 257E29168

Abstract:

In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.