Chih Hsin Wang

US Patent:

6566706, May 20, 2003

Filed:

Oct 31, 2001

Appl. No.:

10/040724

Inventors:

Chih Hsin Wang - San Jose CA
Amitay Levi - Cupertino CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257315, 257239, 257261, 257316, 257317, 257318, 257319, 257320, 257321, 257322, 257323

Abstract:

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. A first plurality of conductive metal contacts are each connected to one of the word lines in one of the word line strap cells. A second plurality of conductive metal contacts are each connected to one of the source lines in one of the source line strap cells.

US Patent:

6541324, Apr 1, 2003

Filed:

Apr 30, 2002

Appl. No.:

10/136797

Inventors:

Chih Hsin Wang - San Jose CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 218247

US Classification:

438201, 438258, 438594

Abstract:

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array and a peripheral region adjacent the array containing related logic devices. Structure planarization is enhanced by utilizing a pattern of dummy material in the peripheral region. The control gates of the memory cells and the logic gates of the logic devices are formed separately so each can be independently optimized.

US Patent:

6580642, Jun 17, 2003

Filed:

Apr 29, 2002

Appl. No.:

10/135916

Inventors:

Chih Hsin Wang - San Jose CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518518, 257214, 257316

Abstract:

A method of erasing a non volatile memory cell having a floating gate disposed over and insulated from a semiconductor substrate by a gate insulation layer, a grid electrode disposed over and insulated from the floating gate, and an injector electrode disposed over and insulated from the grid electrode. The substrate includes source and drain regions with a channel region defined therebetween. The method includes the steps of applying a first voltage to the substrate, and applying a second voltage to the grid electrode and to the injector electrode, wherein the first voltage is sufficiently more positive with respect to the second voltage to induce electrons on the floating gate to tunnel through the gate insulation layer to the substrate via Fowler-Nordheim tunneling.

US Patent:

6627942, Sep 30, 2003

Filed:

Jul 26, 2001

Appl. No.:

09/916423

Inventors:

Chih Hsin Wang - San Jose CA

Assignee:

Silicon Storage Technology, Inc - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257315, 257317, 257314

Abstract:

Method and apparatus for isolating active regions in an electrically programmable and erasable memory device. A first layer of insulating material is formed on a substrate. A layer of conductive material is formed on the first layer of insulating material. A plurality of spaced apart trenches are formed through the first layer of insulating material, the layer of conductive material, and into the substrate. A second layer of insulation material is formed on sidewall portions of the trenches. A block of insulation material is formed in the trenches. For each of the trenches, an edge portion of the layer of conductive material extends over and overlaps with the first layer of insulating material and possibly a portion of the insulation material block by a predetermined distance. For each of the trenches, the predetermined distance is selected so that after back end processing is performed to the substrate and the conductive layer, the edge portion of the conductive layer is aligned to the sidewall portion of the isolation trench.

US Patent:

6627946, Sep 30, 2003

Filed:

Jul 26, 2001

Appl. No.:

09/917023

Inventors:

Chih Hsin Wang - San Jose CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257316, 257315, 257320, 257384, 257385, 438264, 438267

Abstract:

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations. The trenches are filled with a conducting material to form blocks of the conducting material that constitute control gates. The trench indentations result in the formation of protruding portions on the control gates that extend over the floating gates.

US Patent:

6727545, Apr 27, 2004

Filed:

Jul 26, 2001

Appl. No.:

09/916555

Inventors:

Chih Hsin Wang - San Jose CA
Amitay Levi - Cupertino CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257321

Abstract:

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.

US Patent:

6743674, Jun 1, 2004

Filed:

Jul 24, 2002

Appl. No.:

10/205289

Inventors:

Chih Hsin Wang - San Jose CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438257, 438258

Abstract:

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. The control gate polysilicon is formed over the substrate, and protected by a layer of protective material, before the formation of other polysilicon elements associated with the memory array, to ensure the proper remove of residual polysilicon stringers.

US Patent:

6756633, Jun 29, 2004

Filed:

Jun 25, 2002

Appl. No.:

10/183834

Inventors:

Chih Hsin Wang - San Jose CA
Bing Yeh - Los Altos Hills CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257317, 257315, 257316, 257321

Abstract:

A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench. An electrically conductive floating gate is formed over and insulated from a portion of the channel region, with a horizontally oriented edge extending therefrom. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion disposed adjacent to and insulated from the floating gate edge.