Christopher Shawn Mccarty

US Patent:

6629229, Sep 30, 2003

Filed:

May 24, 2001

Appl. No.:

09/864760

Inventors:

Christopher J. McCarty - Colorado Springs CO
Stephen B. Johnson - Colorado Springs CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1202

US Classification:

711202, 711206, 711207, 711203, 709238, 709239, 709314

Abstract:

A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.

US Patent:

6842792, Jan 11, 2005

Filed:

Jun 27, 2002

Appl. No.:

10/183670

Inventors:

Stephen B. Johnson - Colorado Springs CO, US
Bradley D. Besmer - Colorado Springs CO, US
Guy W. Kendall - Colorado Springs CO, US
Christopher J. McCarty - Colorado Springs CO, US
Andrew C. Brown - Colorado Springs CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1314

US Classification:

710 5, 710 6, 709232, 711119

Abstract:

An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

US Patent:

6868492, Mar 15, 2005

Filed:

Jul 20, 2001

Appl. No.:

09/910088

Inventors:

Christopher J. McCarty - Colorado Springs CO, US
Stephen B. Johnson - Colorado Springs CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F009/445

US Classification:

713 1, 713 2, 713100, 710 2, 710 3, 710 6, 710 10, 710 36, 710104

Abstract:

Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.

US Patent:

7007036, Feb 28, 2006

Filed:

Mar 28, 2002

Appl. No.:

10/109285

Inventors:

Christopher J. McCarty - Colorado Springs CO, US
Stephen B. Johnson - Colorado Springs CO, US
Brad D. Besmer - Colorado Springs CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 7/00

US Classification:

707102, 707 1, 711114

Abstract:

The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

US Patent:

7111301, Sep 19, 2006

Filed:

Oct 5, 2001

Appl. No.:

09/972330

Inventors:

Stephen B. Johnson - Colorado Springs CO, US
Christopher J. McCarty - Colorado Springs CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 9/46
G06F 3/06

US Classification:

718105, 710 52

Abstract:

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.

US Patent:

7194640, Mar 20, 2007

Filed:

Dec 8, 2003

Appl. No.:

10/730154

Inventors:

Christopher McCarty - Colorado Springs CO, US
Jeffrey Rogers - Colorado Springs CO, US
Bruce Trunck - Monument CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1/00
G06F 13/00

US Classification:

713300, 711113

Abstract:

The present invention relates to a method, circuit, and system for performing write journal operations on a bus interface controller board or bus interface controller integrated circuit chip. This is achieved by placed a write journal memory on the board or chip and supplying power to it from an external power source. Preferably, the external power source is a battery. The internal memory may use bus interface controller power when available to prolong battery life.

US Patent:

7689744, Mar 30, 2010

Filed:

Mar 17, 2005

Appl. No.:

11/082673

Inventors:

Christopher J. McCarty - Colorado Springs CO, US
Margit C. Evensta - Colorado Springs CO, US
Timothy E. Hoglund - Colorado Springs CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 13/38

US Classification:

710 74, 710 65

Abstract:

Methods and structure for enabling transparent coordination between multiple host systems sharing access to a common SATA storage device to improve bandwidth utilization therebetween in a manner transparent to each of the multiple host systems. The SAS protocol may be utilized by each of the host systems coupled to an SAS/SATA Converter. The storage device coupled to an output path of the SAS/SATA Converter is selectively coupled to one of the multiple host systems each coupled to an input signal path of the SAS/SATA Converter to the shared SATA storage device. Protocol conversion within the SAS/SATA Converter may convert between host SAS protocol exchanges and SATA protocol exchanges of the storage device. Other features within the SAS/SATA Converter may provide queuing or buffering of SAS protocol exchanges from a host system presently non-selected for coupling to the shared SATA storage device.

US Patent:

7913023, Mar 22, 2011

Filed:

Apr 2, 2009

Appl. No.:

12/384287

Inventors:

Stephen B. Johnson - Colorado Springs CO, US
Christopher McCarty - Colorado Springs CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 13/00
G06F 13/40

US Classification:

710307, 710300

Abstract:

The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are checked. The data connection is created on the specified allowable lanes.